1819833afSPeter Tyser /* 2819833afSPeter Tyser * Cross Bar Switch Internal Memory Map 3819833afSPeter Tyser * 4819833afSPeter Tyser * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5819833afSPeter Tyser * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6819833afSPeter Tyser * 7*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8819833afSPeter Tyser */ 9819833afSPeter Tyser 10819833afSPeter Tyser #ifndef __CROSSBAR_H__ 11819833afSPeter Tyser #define __CROSSBAR_H__ 12819833afSPeter Tyser 13819833afSPeter Tyser /********************************************************************* 14819833afSPeter Tyser * Cross-bar switch (XBS) 15819833afSPeter Tyser *********************************************************************/ 16819833afSPeter Tyser typedef struct xbs { 17819833afSPeter Tyser u32 prs1; /* 0x100 Priority Register Slave 1 */ 18819833afSPeter Tyser u32 res1[3]; /* 0x104 - 0F */ 19819833afSPeter Tyser u32 crs1; /* 0x110 Control Register Slave 1 */ 20819833afSPeter Tyser u32 res2[187]; /* 0x114 - 0x3FF */ 21819833afSPeter Tyser 22819833afSPeter Tyser u32 prs4; /* 0x400 Priority Register Slave 4 */ 23819833afSPeter Tyser u32 res3[3]; /* 0x404 - 0F */ 24819833afSPeter Tyser u32 crs4; /* 0x410 Control Register Slave 4 */ 25819833afSPeter Tyser u32 res4[123]; /* 0x414 - 0x5FF */ 26819833afSPeter Tyser 27819833afSPeter Tyser u32 prs6; /* 0x600 Priority Register Slave 6 */ 28819833afSPeter Tyser u32 res5[3]; /* 0x604 - 0F */ 29819833afSPeter Tyser u32 crs6; /* 0x610 Control Register Slave 6 */ 30819833afSPeter Tyser u32 res6[59]; /* 0x614 - 0x6FF */ 31819833afSPeter Tyser 32819833afSPeter Tyser u32 prs7; /* 0x700 Priority Register Slave 7 */ 33819833afSPeter Tyser u32 res7[3]; /* 0x704 - 0F */ 34819833afSPeter Tyser u32 crs7; /* 0x710 Control Register Slave 7 */ 35819833afSPeter Tyser } xbs_t; 36819833afSPeter Tyser 37819833afSPeter Tyser /* Bit definitions and macros for PRS group */ 38819833afSPeter Tyser #define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */ 39819833afSPeter Tyser #define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */ 40819833afSPeter Tyser #define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */ 41819833afSPeter Tyser #define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */ 42819833afSPeter Tyser #define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */ 43819833afSPeter Tyser #define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */ 44819833afSPeter Tyser #define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */ 45819833afSPeter Tyser 46819833afSPeter Tyser /* Bit definitions and macros for CRS group */ 47819833afSPeter Tyser #define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */ 48819833afSPeter Tyser #define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */ 49819833afSPeter Tyser #define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */ 50819833afSPeter Tyser #define XBS_CRS_RO (0x80000000) /* Read Only */ 51819833afSPeter Tyser 52819833afSPeter Tyser #define XBS_CRS_PCTL_PARK_FIELD (0) 53819833afSPeter Tyser #define XBS_CRS_PCTL_PARK_ON_LAST (1) 54819833afSPeter Tyser #define XBS_CRS_PCTL_PARK_NONE (2) 55819833afSPeter Tyser #define XBS_CRS_PCTL_PARK_CORE (0) 56819833afSPeter Tyser #define XBS_CRS_PCTL_PARK_EDMA (1) 57819833afSPeter Tyser #define XBS_CRS_PCTL_PARK_FEC0 (2) 58819833afSPeter Tyser #define XBS_CRS_PCTL_PARK_FEC1 (3) 59819833afSPeter Tyser #define XBS_CRS_PCTL_PARK_PCI (5) 60819833afSPeter Tyser #define XBS_CRS_PCTL_PARK_USB (6) 61819833afSPeter Tyser #define XBS_CRS_PCTL_PARK_SBF (7) 62819833afSPeter Tyser 63819833afSPeter Tyser #endif /* __CROSSBAR_H__ */ 64