1a4145534SPeter Tyser /* 2a4145534SPeter Tyser * 3c6d88630SAlison Wang * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 4a4145534SPeter Tyser * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 5a4145534SPeter Tyser * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7a4145534SPeter Tyser */ 8a4145534SPeter Tyser 9a4145534SPeter Tyser /* CPU specific interrupt routine */ 10a4145534SPeter Tyser #include <common.h> 11a4145534SPeter Tyser #include <asm/immap.h> 12c6d88630SAlison Wang #include <asm/io.h> 13a4145534SPeter Tyser interrupt_init(void)14a4145534SPeter Tyserint interrupt_init(void) 15a4145534SPeter Tyser { 16c6d88630SAlison Wang int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); 17a4145534SPeter Tyser 18a4145534SPeter Tyser /* Make sure all interrupts are disabled */ 19c6d88630SAlison Wang setbits_be32(&intp->imrl0, 0x1); 20a4145534SPeter Tyser 21a4145534SPeter Tyser enable_interrupts(); 22a4145534SPeter Tyser return 0; 23a4145534SPeter Tyser } 24a4145534SPeter Tyser 25a4145534SPeter Tyser #if defined(CONFIG_MCFTMR) dtimer_intr_setup(void)26a4145534SPeter Tyservoid dtimer_intr_setup(void) 27a4145534SPeter Tyser { 28c6d88630SAlison Wang int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); 29a4145534SPeter Tyser 30c6d88630SAlison Wang out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); 31c6d88630SAlison Wang clrbits_be32(&intp->imrl0, INTC_IPRL_INT0); 32c6d88630SAlison Wang clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK); 33a4145534SPeter Tyser } 34a4145534SPeter Tyser #endif 35