1*9b9c6516SMasahiro Yamada /* 2*9b9c6516SMasahiro Yamada * Copyright (c) 2013 Xilinx Inc. 3*9b9c6516SMasahiro Yamada * 4*9b9c6516SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 5*9b9c6516SMasahiro Yamada */ 6*9b9c6516SMasahiro Yamada 7*9b9c6516SMasahiro Yamada #ifndef _ZYNQ_CLK_H_ 8*9b9c6516SMasahiro Yamada #define _ZYNQ_CLK_H_ 9*9b9c6516SMasahiro Yamada 10*9b9c6516SMasahiro Yamada enum zynq_clk { 11*9b9c6516SMasahiro Yamada armpll_clk, ddrpll_clk, iopll_clk, 12*9b9c6516SMasahiro Yamada cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk, 13*9b9c6516SMasahiro Yamada ddr2x_clk, ddr3x_clk, dci_clk, 14*9b9c6516SMasahiro Yamada lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk, 15*9b9c6516SMasahiro Yamada fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk, 16*9b9c6516SMasahiro Yamada sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk, 17*9b9c6516SMasahiro Yamada usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk, 18*9b9c6516SMasahiro Yamada sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk, 19*9b9c6516SMasahiro Yamada can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk, 20*9b9c6516SMasahiro Yamada uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk, 21*9b9c6516SMasahiro Yamada smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max}; 22*9b9c6516SMasahiro Yamada 23*9b9c6516SMasahiro Yamada #endif 24