1*63637a48SMasahiro Yamada /* 2*63637a48SMasahiro Yamada * (C) Copyright 2003 3*63637a48SMasahiro Yamada * Texas Instruments <www.ti.com> 4*63637a48SMasahiro Yamada * 5*63637a48SMasahiro Yamada * (C) Copyright 2002 6*63637a48SMasahiro Yamada * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7*63637a48SMasahiro Yamada * Marius Groeger <mgroeger@sysgo.de> 8*63637a48SMasahiro Yamada * 9*63637a48SMasahiro Yamada * (C) Copyright 2002 10*63637a48SMasahiro Yamada * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 11*63637a48SMasahiro Yamada * Alex Zuepke <azu@sysgo.de> 12*63637a48SMasahiro Yamada * 13*63637a48SMasahiro Yamada * (C) Copyright 2002-2004 14*63637a48SMasahiro Yamada * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> 15*63637a48SMasahiro Yamada * 16*63637a48SMasahiro Yamada * (C) Copyright 2004 17*63637a48SMasahiro Yamada * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> 18*63637a48SMasahiro Yamada * 19*63637a48SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 20*63637a48SMasahiro Yamada */ 21*63637a48SMasahiro Yamada 22*63637a48SMasahiro Yamada #include <common.h> 23*63637a48SMasahiro Yamada 24*63637a48SMasahiro Yamada #define TIMER_ENABLE (1 << 7) 25*63637a48SMasahiro Yamada #define TIMER_MODE_MSK (1 << 6) 26*63637a48SMasahiro Yamada #define TIMER_MODE_FR (0 << 6) 27*63637a48SMasahiro Yamada #define TIMER_MODE_PD (1 << 6) 28*63637a48SMasahiro Yamada 29*63637a48SMasahiro Yamada #define TIMER_INT_EN (1 << 5) 30*63637a48SMasahiro Yamada #define TIMER_PRS_MSK (3 << 2) 31*63637a48SMasahiro Yamada #define TIMER_PRS_8S (1 << 3) 32*63637a48SMasahiro Yamada #define TIMER_SIZE_MSK (1 << 2) 33*63637a48SMasahiro Yamada #define TIMER_ONE_SHT (1 << 0) 34*63637a48SMasahiro Yamada timer_init(void)35*63637a48SMasahiro Yamadaint timer_init (void) 36*63637a48SMasahiro Yamada { 37*63637a48SMasahiro Yamada ulong tmr_ctrl_val; 38*63637a48SMasahiro Yamada 39*63637a48SMasahiro Yamada /* 1st disable the Timer */ 40*63637a48SMasahiro Yamada tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); 41*63637a48SMasahiro Yamada tmr_ctrl_val &= ~TIMER_ENABLE; 42*63637a48SMasahiro Yamada *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; 43*63637a48SMasahiro Yamada 44*63637a48SMasahiro Yamada /* 45*63637a48SMasahiro Yamada * The Timer Control Register has one Undefined/Shouldn't Use Bit 46*63637a48SMasahiro Yamada * So we should do read/modify/write Operation 47*63637a48SMasahiro Yamada */ 48*63637a48SMasahiro Yamada 49*63637a48SMasahiro Yamada /* 50*63637a48SMasahiro Yamada * Timer Mode : Free Running 51*63637a48SMasahiro Yamada * Interrupt : Disabled 52*63637a48SMasahiro Yamada * Prescale : 8 Stage, Clk/256 53*63637a48SMasahiro Yamada * Tmr Siz : 16 Bit Counter 54*63637a48SMasahiro Yamada * Tmr in Wrapping Mode 55*63637a48SMasahiro Yamada */ 56*63637a48SMasahiro Yamada tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); 57*63637a48SMasahiro Yamada tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); 58*63637a48SMasahiro Yamada tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); 59*63637a48SMasahiro Yamada 60*63637a48SMasahiro Yamada *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; 61*63637a48SMasahiro Yamada 62*63637a48SMasahiro Yamada return 0; 63*63637a48SMasahiro Yamada } 64*63637a48SMasahiro Yamada 65