xref: /rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/dpll-tail.c (revision 9a6535e05f17acf03e891266a650cb6029124743) 
1*6a3e4274SMasahiro Yamada /*
2*6a3e4274SMasahiro Yamada  * Copyright (C) 2011-2014 Panasonic Corporation
3*6a3e4274SMasahiro Yamada  * Copyright (C) 2015-2016 Socionext Inc.
4*6a3e4274SMasahiro Yamada  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5*6a3e4274SMasahiro Yamada  *
6*6a3e4274SMasahiro Yamada  * SPDX-License-Identifier:	GPL-2.0+
7*6a3e4274SMasahiro Yamada  */
8*6a3e4274SMasahiro Yamada 
9*6a3e4274SMasahiro Yamada #include <linux/io.h>
10*6a3e4274SMasahiro Yamada 
11*6a3e4274SMasahiro Yamada #include "../sc-regs.h"
12*6a3e4274SMasahiro Yamada #include "pll.h"
13*6a3e4274SMasahiro Yamada 
uniphier_ld4_dpll_ssc_en(void)14*6a3e4274SMasahiro Yamada void uniphier_ld4_dpll_ssc_en(void)
15*6a3e4274SMasahiro Yamada {
16*6a3e4274SMasahiro Yamada 	u32 tmp;
17*6a3e4274SMasahiro Yamada 
18*6a3e4274SMasahiro Yamada 	tmp = readl(SC_DPLLCTRL);
19*6a3e4274SMasahiro Yamada 	tmp |= SC_DPLLCTRL_SSC_EN;
20*6a3e4274SMasahiro Yamada 	writel(tmp, SC_DPLLCTRL);
21*6a3e4274SMasahiro Yamada }
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