1fcc238baSMasahiro Yamada /* 2fcc238baSMasahiro Yamada * Copyright (C) 2013-2014 Panasonic Corporation 3fcc238baSMasahiro Yamada * Copyright (C) 2015-2016 Socionext Inc. 4fcc238baSMasahiro Yamada * 5fcc238baSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 6fcc238baSMasahiro Yamada */ 7fcc238baSMasahiro Yamada 8fcc238baSMasahiro Yamada #include <common.h> 9*0f4ec05bSMasahiro Yamada #include <linux/errno.h> 10fcc238baSMasahiro Yamada #include <linux/io.h> 11fcc238baSMasahiro Yamada 12fcc238baSMasahiro Yamada #include "../init.h" 13fcc238baSMasahiro Yamada #include "../sc-regs.h" 14fcc238baSMasahiro Yamada 15fcc238baSMasahiro Yamada #undef DPLL_SSC_RATE_1PER 16fcc238baSMasahiro Yamada uniphier_ld4_dpll_init(const struct uniphier_board_data * bd)17fcc238baSMasahiro Yamadaint uniphier_ld4_dpll_init(const struct uniphier_board_data *bd) 18fcc238baSMasahiro Yamada { 19fcc238baSMasahiro Yamada unsigned int dram_freq = bd->dram_freq; 20fcc238baSMasahiro Yamada u32 tmp; 21fcc238baSMasahiro Yamada 22fcc238baSMasahiro Yamada /* 23fcc238baSMasahiro Yamada * Set Frequency 24fcc238baSMasahiro Yamada * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) 25fcc238baSMasahiro Yamada * to FOUT (DPLLCTRL.bit[29:20]) 26fcc238baSMasahiro Yamada */ 27fcc238baSMasahiro Yamada tmp = readl(SC_DPLLCTRL); 28fcc238baSMasahiro Yamada tmp &= ~0x000f0000; 29fcc238baSMasahiro Yamada switch (dram_freq) { 30fcc238baSMasahiro Yamada case 1333: 31fcc238baSMasahiro Yamada tmp |= 0x000d0000; 32fcc238baSMasahiro Yamada break; 33fcc238baSMasahiro Yamada case 1600: 34fcc238baSMasahiro Yamada tmp |= 0x000c0000; 35fcc238baSMasahiro Yamada break; 36fcc238baSMasahiro Yamada default: 37fcc238baSMasahiro Yamada pr_err("Unsupported frequency"); 38fcc238baSMasahiro Yamada return -EINVAL; 39fcc238baSMasahiro Yamada } 40fcc238baSMasahiro Yamada 41fcc238baSMasahiro Yamada #if defined(DPLL_SSC_RATE_1PER) 42fcc238baSMasahiro Yamada tmp &= ~SC_DPLLCTRL_SSC_RATE; 43fcc238baSMasahiro Yamada #else 44fcc238baSMasahiro Yamada tmp |= SC_DPLLCTRL_SSC_RATE; 45fcc238baSMasahiro Yamada #endif 46fcc238baSMasahiro Yamada writel(tmp, SC_DPLLCTRL); 47fcc238baSMasahiro Yamada 48fcc238baSMasahiro Yamada tmp = readl(SC_DPLLCTRL2); 49fcc238baSMasahiro Yamada tmp |= SC_DPLLCTRL2_NRSTDS; 50fcc238baSMasahiro Yamada writel(tmp, SC_DPLLCTRL2); 51fcc238baSMasahiro Yamada 52fcc238baSMasahiro Yamada /* Wait 500 usec until dpll gets stable */ 53fcc238baSMasahiro Yamada udelay(500); 54fcc238baSMasahiro Yamada 55fcc238baSMasahiro Yamada return 0; 56fcc238baSMasahiro Yamada } 57