xref: /rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c (revision bfd07670a48d9fbf22646c93e07dcd8cbc8d0864)
1*78c627cfSMasahiro Yamada /*
2*78c627cfSMasahiro Yamada  * Copyright (C) 2016-2017 Socionext Inc.
3*78c627cfSMasahiro Yamada  *
4*78c627cfSMasahiro Yamada  * SPDX-License-Identifier:	GPL-2.0+
5*78c627cfSMasahiro Yamada  */
6*78c627cfSMasahiro Yamada 
7*78c627cfSMasahiro Yamada #include <common.h>
8*78c627cfSMasahiro Yamada #include <spl.h>
9*78c627cfSMasahiro Yamada #include <linux/io.h>
10*78c627cfSMasahiro Yamada 
11*78c627cfSMasahiro Yamada #include "../init.h"
12*78c627cfSMasahiro Yamada #include "../sc-regs.h"
13*78c627cfSMasahiro Yamada 
uniphier_pxs2_dram_clk_init(void)14*78c627cfSMasahiro Yamada void uniphier_pxs2_dram_clk_init(void)
15*78c627cfSMasahiro Yamada {
16*78c627cfSMasahiro Yamada 	u32 tmp;
17*78c627cfSMasahiro Yamada 
18*78c627cfSMasahiro Yamada 	/* deassert reset */
19*78c627cfSMasahiro Yamada 	tmp = readl(SC_RSTCTRL4);
20*78c627cfSMasahiro Yamada 	tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
21*78c627cfSMasahiro Yamada 	       SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
22*78c627cfSMasahiro Yamada 	       SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
23*78c627cfSMasahiro Yamada 	       SC_RSTCTRL4_NRST_UMC30;
24*78c627cfSMasahiro Yamada 	writel(tmp, SC_RSTCTRL4);
25*78c627cfSMasahiro Yamada 	readl(SC_RSTCTRL4); /* dummy read */
26*78c627cfSMasahiro Yamada 
27*78c627cfSMasahiro Yamada 	/* provide clocks */
28*78c627cfSMasahiro Yamada 	tmp = readl(SC_CLKCTRL4);
29*78c627cfSMasahiro Yamada 	tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
30*78c627cfSMasahiro Yamada 	       SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
31*78c627cfSMasahiro Yamada 	writel(tmp, SC_CLKCTRL4);
32*78c627cfSMasahiro Yamada 	readl(SC_CLKCTRL4); /* dummy read */
33*78c627cfSMasahiro Yamada }
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