1 /* 2 * Copyright (C) 2012-2015 Panasonic Corporation 3 * Copyright (C) 2015-2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <libfdt.h> 11 #include <linux/io.h> 12 13 #include "init.h" 14 #include "micro-support-card.h" 15 #include "sg-regs.h" 16 #include "soc-info.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 static void uniphier_setup_xirq(void) 21 { 22 const void *fdt = gd->fdt_blob; 23 int soc_node, aidet_node; 24 const u32 *val; 25 unsigned long aidet_base; 26 u32 tmp; 27 28 soc_node = fdt_path_offset(fdt, "/soc"); 29 if (soc_node < 0) 30 return; 31 32 aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5); 33 if (aidet_node < 0) 34 return; 35 36 val = fdt_getprop(fdt, aidet_node, "reg", NULL); 37 if (!val) 38 return; 39 40 aidet_base = fdt32_to_cpu(*val); 41 42 tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */ 43 tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */ 44 writel(tmp, aidet_base + 8); 45 46 tmp = readl(0x55000090); /* IRQCTL */ 47 tmp |= 0x000000ff; 48 writel(tmp, 0x55000090); 49 } 50 51 static void uniphier_nand_pin_init(bool cs2) 52 { 53 #ifdef CONFIG_NAND_DENALI 54 if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp")) 55 pr_err("failed to init NAND pins\n"); 56 #endif 57 } 58 59 int board_init(void) 60 { 61 led_puts("U0"); 62 63 switch (uniphier_get_soc_type()) { 64 #if defined(CONFIG_ARCH_UNIPHIER_SLD3) 65 case SOC_UNIPHIER_SLD3: 66 uniphier_nand_pin_init(true); 67 led_puts("U1"); 68 uniphier_sld3_pll_init(); 69 uniphier_ld4_clk_init(); 70 break; 71 #endif 72 #if defined(CONFIG_ARCH_UNIPHIER_LD4) 73 case SOC_UNIPHIER_LD4: 74 uniphier_nand_pin_init(true); 75 led_puts("U1"); 76 uniphier_ld4_pll_init(); 77 uniphier_ld4_clk_init(); 78 break; 79 #endif 80 #if defined(CONFIG_ARCH_UNIPHIER_PRO4) 81 case SOC_UNIPHIER_PRO4: 82 uniphier_nand_pin_init(false); 83 led_puts("U1"); 84 uniphier_pro4_pll_init(); 85 uniphier_pro4_clk_init(); 86 break; 87 #endif 88 #if defined(CONFIG_ARCH_UNIPHIER_SLD8) 89 case SOC_UNIPHIER_SLD8: 90 uniphier_nand_pin_init(true); 91 led_puts("U1"); 92 uniphier_ld4_pll_init(); 93 uniphier_ld4_clk_init(); 94 break; 95 #endif 96 #if defined(CONFIG_ARCH_UNIPHIER_PRO5) 97 case SOC_UNIPHIER_PRO5: 98 uniphier_nand_pin_init(true); 99 led_puts("U1"); 100 uniphier_pro5_clk_init(); 101 break; 102 #endif 103 #if defined(CONFIG_ARCH_UNIPHIER_PXS2) 104 case SOC_UNIPHIER_PXS2: 105 uniphier_nand_pin_init(true); 106 led_puts("U1"); 107 uniphier_pxs2_clk_init(); 108 break; 109 #endif 110 #if defined(CONFIG_ARCH_UNIPHIER_LD6B) 111 case SOC_UNIPHIER_LD6B: 112 uniphier_nand_pin_init(true); 113 led_puts("U1"); 114 uniphier_pxs2_clk_init(); 115 break; 116 #endif 117 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 118 case SOC_UNIPHIER_LD11: 119 uniphier_nand_pin_init(false); 120 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ 121 sg_set_iectrl(149); 122 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ 123 sg_set_iectrl(153); 124 led_puts("U1"); 125 uniphier_ld11_pll_init(); 126 uniphier_ld11_clk_init(); 127 break; 128 #endif 129 #if defined(CONFIG_ARCH_UNIPHIER_LD20) 130 case SOC_UNIPHIER_LD20: 131 /* ES1 errata: increase VDD09 supply to suppress VBO noise */ 132 if (uniphier_get_soc_revision() == 1) { 133 writel(0x00000003, 0x6184e004); 134 writel(0x00000100, 0x6184e040); 135 writel(0x0000b500, 0x6184e024); 136 writel(0x00000001, 0x6184e000); 137 } 138 uniphier_nand_pin_init(false); 139 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ 140 sg_set_iectrl(149); 141 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ 142 sg_set_iectrl(153); 143 led_puts("U1"); 144 uniphier_ld20_pll_init(); 145 uniphier_ld20_clk_init(); 146 cci500_init(2); 147 break; 148 #endif 149 default: 150 break; 151 } 152 153 uniphier_setup_xirq(); 154 155 led_puts("U2"); 156 157 support_card_late_init(); 158 159 led_puts("U3"); 160 161 #ifdef CONFIG_ARM64 162 uniphier_smp_kick_all_cpus(); 163 #endif 164 165 led_puts("Uboo"); 166 167 return 0; 168 } 169