1*fe5ea57bSMasahiro Yamada/* 2*fe5ea57bSMasahiro Yamada * On-chip UART initializaion for low-level debugging 3*fe5ea57bSMasahiro Yamada * 4*fe5ea57bSMasahiro Yamada * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> 5*fe5ea57bSMasahiro Yamada * 6*fe5ea57bSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 7*fe5ea57bSMasahiro Yamada */ 8*fe5ea57bSMasahiro Yamada 9*fe5ea57bSMasahiro Yamada#include <linux/serial_reg.h> 10*fe5ea57bSMasahiro Yamada#include <linux/linkage.h> 11*fe5ea57bSMasahiro Yamada 12*fe5ea57bSMasahiro Yamada#include "../bcu/bcu-regs.h" 13*fe5ea57bSMasahiro Yamada#include "../sc-regs.h" 14*fe5ea57bSMasahiro Yamada#include "../sg-regs.h" 15*fe5ea57bSMasahiro Yamada 16*fe5ea57bSMasahiro Yamada#if !defined(CONFIG_DEBUG_SEMIHOSTING) 17*fe5ea57bSMasahiro Yamada#include CONFIG_DEBUG_LL_INCLUDE 18*fe5ea57bSMasahiro Yamada#endif 19*fe5ea57bSMasahiro Yamada 20*fe5ea57bSMasahiro Yamada#define BAUDRATE 115200 21*fe5ea57bSMasahiro Yamada#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) 22*fe5ea57bSMasahiro Yamada 23*fe5ea57bSMasahiro YamadaENTRY(debug_ll_init) 24*fe5ea57bSMasahiro Yamada ldr r0, =SG_REVISION 25*fe5ea57bSMasahiro Yamada ldr r1, [r0] 26*fe5ea57bSMasahiro Yamada and r1, r1, #SG_REVISION_TYPE_MASK 27*fe5ea57bSMasahiro Yamada mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT 28*fe5ea57bSMasahiro Yamada 29*fe5ea57bSMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) 30*fe5ea57bSMasahiro Yamada#define PH1_SLD3_UART_CLK 36864000 31*fe5ea57bSMasahiro Yamada cmp r1, #0x25 32*fe5ea57bSMasahiro Yamada bne ph1_sld3_end 33*fe5ea57bSMasahiro Yamada 34*fe5ea57bSMasahiro Yamada sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0 35*fe5ea57bSMasahiro Yamada 36*fe5ea57bSMasahiro Yamada ldr r0, =BCSCR5 37*fe5ea57bSMasahiro Yamada ldr r1, =0x24440000 38*fe5ea57bSMasahiro Yamada str r1, [r0] 39*fe5ea57bSMasahiro Yamada 40*fe5ea57bSMasahiro Yamada ldr r0, =SC_CLKCTRL 41*fe5ea57bSMasahiro Yamada ldr r1, [r0] 42*fe5ea57bSMasahiro Yamada orr r1, r1, #SC_CLKCTRL_CEN_PERI 43*fe5ea57bSMasahiro Yamada str r1, [r0] 44*fe5ea57bSMasahiro Yamada 45*fe5ea57bSMasahiro Yamada ldr r3, =DIV_ROUND(PH1_SLD3_UART_CLK, 16 * BAUDRATE) 46*fe5ea57bSMasahiro Yamada 47*fe5ea57bSMasahiro Yamada b init_uart 48*fe5ea57bSMasahiro Yamadaph1_sld3_end: 49*fe5ea57bSMasahiro Yamada#endif 50*fe5ea57bSMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) 51*fe5ea57bSMasahiro Yamada#define PH1_LD4_UART_CLK 36864000 52*fe5ea57bSMasahiro Yamada cmp r1, #0x26 53*fe5ea57bSMasahiro Yamada bne ph1_ld4_end 54*fe5ea57bSMasahiro Yamada 55*fe5ea57bSMasahiro Yamada ldr r0, =SG_IECTRL 56*fe5ea57bSMasahiro Yamada ldr r1, [r0] 57*fe5ea57bSMasahiro Yamada orr r1, r1, #1 58*fe5ea57bSMasahiro Yamada str r1, [r0] 59*fe5ea57bSMasahiro Yamada 60*fe5ea57bSMasahiro Yamada sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0 61*fe5ea57bSMasahiro Yamada 62*fe5ea57bSMasahiro Yamada ldr r3, =DIV_ROUND(PH1_LD4_UART_CLK, 16 * BAUDRATE) 63*fe5ea57bSMasahiro Yamada 64*fe5ea57bSMasahiro Yamada b init_uart 65*fe5ea57bSMasahiro Yamadaph1_ld4_end: 66*fe5ea57bSMasahiro Yamada#endif 67*fe5ea57bSMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) 68*fe5ea57bSMasahiro Yamada#define PH1_PRO4_UART_CLK 73728000 69*fe5ea57bSMasahiro Yamada cmp r1, #0x28 70*fe5ea57bSMasahiro Yamada bne ph1_pro4_end 71*fe5ea57bSMasahiro Yamada 72*fe5ea57bSMasahiro Yamada sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 73*fe5ea57bSMasahiro Yamada 74*fe5ea57bSMasahiro Yamada ldr r0, =SG_LOADPINCTRL 75*fe5ea57bSMasahiro Yamada mov r1, #1 76*fe5ea57bSMasahiro Yamada str r1, [r0] 77*fe5ea57bSMasahiro Yamada 78*fe5ea57bSMasahiro Yamada ldr r0, =SC_CLKCTRL 79*fe5ea57bSMasahiro Yamada ldr r1, [r0] 80*fe5ea57bSMasahiro Yamada orr r1, r1, #SC_CLKCTRL_CEN_PERI 81*fe5ea57bSMasahiro Yamada str r1, [r0] 82*fe5ea57bSMasahiro Yamada 83*fe5ea57bSMasahiro Yamada ldr r3, =DIV_ROUND(PH1_PRO4_UART_CLK, 16 * BAUDRATE) 84*fe5ea57bSMasahiro Yamada 85*fe5ea57bSMasahiro Yamada b init_uart 86*fe5ea57bSMasahiro Yamadaph1_pro4_end: 87*fe5ea57bSMasahiro Yamada#endif 88*fe5ea57bSMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) 89*fe5ea57bSMasahiro Yamada#define PH1_SLD8_UART_CLK 80000000 90*fe5ea57bSMasahiro Yamada cmp r1, #0x29 91*fe5ea57bSMasahiro Yamada bne ph1_sld8_end 92*fe5ea57bSMasahiro Yamada 93*fe5ea57bSMasahiro Yamada ldr r0, =SG_IECTRL 94*fe5ea57bSMasahiro Yamada ldr r1, [r0] 95*fe5ea57bSMasahiro Yamada orr r1, r1, #1 96*fe5ea57bSMasahiro Yamada str r1, [r0] 97*fe5ea57bSMasahiro Yamada 98*fe5ea57bSMasahiro Yamada sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0 99*fe5ea57bSMasahiro Yamada 100*fe5ea57bSMasahiro Yamada ldr r3, =DIV_ROUND(PH1_SLD8_UART_CLK, 16 * BAUDRATE) 101*fe5ea57bSMasahiro Yamada 102*fe5ea57bSMasahiro Yamada b init_uart 103*fe5ea57bSMasahiro Yamadaph1_sld8_end: 104*fe5ea57bSMasahiro Yamada#endif 105*fe5ea57bSMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5) 106*fe5ea57bSMasahiro Yamada#define PH1_PRO5_UART_CLK 73728000 107*fe5ea57bSMasahiro Yamada cmp r1, #0x2A 108*fe5ea57bSMasahiro Yamada bne ph1_pro5_end 109*fe5ea57bSMasahiro Yamada 110*fe5ea57bSMasahiro Yamada sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 111*fe5ea57bSMasahiro Yamada sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1 112*fe5ea57bSMasahiro Yamada sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2 113*fe5ea57bSMasahiro Yamada sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3 114*fe5ea57bSMasahiro Yamada 115*fe5ea57bSMasahiro Yamada ldr r0, =SG_LOADPINCTRL 116*fe5ea57bSMasahiro Yamada mov r1, #1 117*fe5ea57bSMasahiro Yamada str r1, [r0] 118*fe5ea57bSMasahiro Yamada 119*fe5ea57bSMasahiro Yamada ldr r0, =SC_CLKCTRL 120*fe5ea57bSMasahiro Yamada ldr r1, [r0] 121*fe5ea57bSMasahiro Yamada orr r1, r1, #SC_CLKCTRL_CEN_PERI 122*fe5ea57bSMasahiro Yamada str r1, [r0] 123*fe5ea57bSMasahiro Yamada 124*fe5ea57bSMasahiro Yamada ldr r3, =DIV_ROUND(PH1_PRO5_UART_CLK, 16 * BAUDRATE) 125*fe5ea57bSMasahiro Yamada 126*fe5ea57bSMasahiro Yamada b init_uart 127*fe5ea57bSMasahiro Yamadaph1_pro5_end: 128*fe5ea57bSMasahiro Yamada#endif 129*fe5ea57bSMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) 130*fe5ea57bSMasahiro Yamada#define PROXSTREAM2_UART_CLK 88900000 131*fe5ea57bSMasahiro Yamada cmp r1, #0x2E 132*fe5ea57bSMasahiro Yamada bne proxstream2_end 133*fe5ea57bSMasahiro Yamada 134*fe5ea57bSMasahiro Yamada ldr r0, =SG_IECTRL 135*fe5ea57bSMasahiro Yamada ldr r1, [r0] 136*fe5ea57bSMasahiro Yamada orr r1, r1, #1 137*fe5ea57bSMasahiro Yamada str r1, [r0] 138*fe5ea57bSMasahiro Yamada 139*fe5ea57bSMasahiro Yamada sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0 140*fe5ea57bSMasahiro Yamada sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1 141*fe5ea57bSMasahiro Yamada sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2 142*fe5ea57bSMasahiro Yamada sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3 143*fe5ea57bSMasahiro Yamada 144*fe5ea57bSMasahiro Yamada ldr r0, =SC_CLKCTRL 145*fe5ea57bSMasahiro Yamada ldr r1, [r0] 146*fe5ea57bSMasahiro Yamada orr r1, r1, #SC_CLKCTRL_CEN_PERI 147*fe5ea57bSMasahiro Yamada str r1, [r0] 148*fe5ea57bSMasahiro Yamada 149*fe5ea57bSMasahiro Yamada ldr r3, =DIV_ROUND(PROXSTREAM2_UART_CLK, 16 * BAUDRATE) 150*fe5ea57bSMasahiro Yamada 151*fe5ea57bSMasahiro Yamada b init_uart 152*fe5ea57bSMasahiro Yamadaproxstream2_end: 153*fe5ea57bSMasahiro Yamada#endif 154*fe5ea57bSMasahiro Yamada#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) 155*fe5ea57bSMasahiro Yamada#define PH1_LD6B_UART_CLK 88900000 156*fe5ea57bSMasahiro Yamada cmp r1, #0x2F 157*fe5ea57bSMasahiro Yamada bne ph1_ld6b_end 158*fe5ea57bSMasahiro Yamada 159*fe5ea57bSMasahiro Yamada ldr r0, =SG_IECTRL 160*fe5ea57bSMasahiro Yamada ldr r1, [r0] 161*fe5ea57bSMasahiro Yamada orr r1, r1, #1 162*fe5ea57bSMasahiro Yamada str r1, [r0] 163*fe5ea57bSMasahiro Yamada 164*fe5ea57bSMasahiro Yamada sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0 165*fe5ea57bSMasahiro Yamada sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1 166*fe5ea57bSMasahiro Yamada sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2 167*fe5ea57bSMasahiro Yamada 168*fe5ea57bSMasahiro Yamada ldr r0, =SC_CLKCTRL 169*fe5ea57bSMasahiro Yamada ldr r1, [r0] 170*fe5ea57bSMasahiro Yamada orr r1, r1, #SC_CLKCTRL_CEN_PERI 171*fe5ea57bSMasahiro Yamada str r1, [r0] 172*fe5ea57bSMasahiro Yamada 173*fe5ea57bSMasahiro Yamada ldr r3, =DIV_ROUND(PH1_LD6B_UART_CLK, 16 * BAUDRATE) 174*fe5ea57bSMasahiro Yamada 175*fe5ea57bSMasahiro Yamada b init_uart 176*fe5ea57bSMasahiro Yamadaph1_ld6b_end: 177*fe5ea57bSMasahiro Yamada#endif 178*fe5ea57bSMasahiro Yamada 179*fe5ea57bSMasahiro Yamadainit_uart: 180*fe5ea57bSMasahiro Yamada addruart r0, r1, r2 181*fe5ea57bSMasahiro Yamada mov r1, #UART_LCR_WLEN8 << 8 182*fe5ea57bSMasahiro Yamada str r1, [r0, #0x10] 183*fe5ea57bSMasahiro Yamada str r3, [r0, #0x24] 184*fe5ea57bSMasahiro Yamada 185*fe5ea57bSMasahiro Yamada mov pc, lr 186*fe5ea57bSMasahiro YamadaENDPROC(debug_ll_init) 187