1fe5ea57bSMasahiro Yamada /* 2fe5ea57bSMasahiro Yamada * Copyright (C) 2011-2014 Panasonic Corporation 3fe5ea57bSMasahiro Yamada * 4fe5ea57bSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 5fe5ea57bSMasahiro Yamada */ 6fe5ea57bSMasahiro Yamada 7fe5ea57bSMasahiro Yamada #ifndef ARCH_ARM_MPCORE_H 8fe5ea57bSMasahiro Yamada #define ARCH_ARM_MPCORE_H 9fe5ea57bSMasahiro Yamada 10fe5ea57bSMasahiro Yamada /* Snoop Control Unit */ 11fe5ea57bSMasahiro Yamada #define SCU_OFFSET 0x00 12fe5ea57bSMasahiro Yamada 13fe5ea57bSMasahiro Yamada /* SCU Control Register */ 14fe5ea57bSMasahiro Yamada #define SCU_CTRL 0x00 15*e8a92932SMasahiro Yamada #define SCU_ENABLE (1 << 0) 16*e8a92932SMasahiro Yamada #define SCU_STANDBY_ENABLE (1 << 5) 17*e8a92932SMasahiro Yamada 18fe5ea57bSMasahiro Yamada /* SCU Configuration Register */ 19fe5ea57bSMasahiro Yamada #define SCU_CONF 0x04 20fe5ea57bSMasahiro Yamada /* SCU CPU Power Status Register */ 21fe5ea57bSMasahiro Yamada #define SCU_PWR_STATUS 0x08 22fe5ea57bSMasahiro Yamada /* SCU Invalidate All Registers in Secure State */ 23fe5ea57bSMasahiro Yamada #define SCU_INV_ALL 0x0C 24fe5ea57bSMasahiro Yamada /* SCU Filtering Start Address Register */ 25fe5ea57bSMasahiro Yamada #define SCU_FILTER_START 0x40 26fe5ea57bSMasahiro Yamada /* SCU Filtering End Address Register */ 27fe5ea57bSMasahiro Yamada #define SCU_FILTER_END 0x44 28fe5ea57bSMasahiro Yamada /* SCU Access Control Register */ 29fe5ea57bSMasahiro Yamada #define SCU_SAC 0x50 30fe5ea57bSMasahiro Yamada /* SCU Non-secure Access Control Register */ 31fe5ea57bSMasahiro Yamada #define SCU_SNSAC 0x54 32fe5ea57bSMasahiro Yamada 33fe5ea57bSMasahiro Yamada /* Global Timer */ 34fe5ea57bSMasahiro Yamada #define GLOBAL_TIMER_OFFSET 0x200 35fe5ea57bSMasahiro Yamada 36fe5ea57bSMasahiro Yamada /* Global Timer Counter Registers */ 37fe5ea57bSMasahiro Yamada #define GTIMER_CNT_L 0x00 38fe5ea57bSMasahiro Yamada #define GTIMER_CNT_H 0x04 39fe5ea57bSMasahiro Yamada /* Global Timer Control Register */ 40fe5ea57bSMasahiro Yamada #define GTIMER_CTRL 0x08 41fe5ea57bSMasahiro Yamada /* Global Timer Interrupt Status Register */ 42fe5ea57bSMasahiro Yamada #define GTIMER_STAT 0x0C 43fe5ea57bSMasahiro Yamada /* Comparator Value Registers */ 44fe5ea57bSMasahiro Yamada #define GTIMER_CMP_L 0x10 45fe5ea57bSMasahiro Yamada #define GTIMER_CMP_H 0x14 46fe5ea57bSMasahiro Yamada /* Auto-increment Register */ 47fe5ea57bSMasahiro Yamada #define GTIMER_INC 0x18 48fe5ea57bSMasahiro Yamada 49fe5ea57bSMasahiro Yamada #endif /* ARCH_ARM_MPCORE_H */ 50