1 /* 2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _TEGRA_XUSB_PADCTL_COMMON_H_ 8 #define _TEGRA_XUSB_PADCTL_COMMON_H_ 9 10 #include <common.h> 11 #include <fdtdec.h> 12 13 #include <asm/io.h> 14 #include <asm/arch-tegra/xusb-padctl.h> 15 16 struct tegra_xusb_padctl_lane { 17 const char *name; 18 19 unsigned int offset; 20 unsigned int shift; 21 unsigned int mask; 22 unsigned int iddq; 23 24 const unsigned int *funcs; 25 unsigned int num_funcs; 26 }; 27 28 struct tegra_xusb_phy_ops { 29 int (*prepare)(struct tegra_xusb_phy *phy); 30 int (*enable)(struct tegra_xusb_phy *phy); 31 int (*disable)(struct tegra_xusb_phy *phy); 32 int (*unprepare)(struct tegra_xusb_phy *phy); 33 }; 34 35 struct tegra_xusb_phy { 36 const struct tegra_xusb_phy_ops *ops; 37 38 struct tegra_xusb_padctl *padctl; 39 }; 40 41 struct tegra_xusb_padctl_pin { 42 const struct tegra_xusb_padctl_lane *lane; 43 44 unsigned int func; 45 int iddq; 46 }; 47 48 #define MAX_GROUPS 3 49 #define MAX_PINS 6 50 51 struct tegra_xusb_padctl_group { 52 const char *name; 53 54 const char *pins[MAX_PINS]; 55 unsigned int num_pins; 56 57 const char *func; 58 int iddq; 59 }; 60 61 struct tegra_xusb_padctl_config { 62 const char *name; 63 64 struct tegra_xusb_padctl_group groups[MAX_GROUPS]; 65 unsigned int num_groups; 66 }; 67 68 struct tegra_xusb_padctl { 69 struct fdt_resource regs; 70 71 unsigned int enable; 72 73 struct tegra_xusb_phy phys[2]; 74 75 const struct tegra_xusb_padctl_lane *lanes; 76 unsigned int num_lanes; 77 78 const char *const *functions; 79 unsigned int num_functions; 80 81 struct tegra_xusb_padctl_config config; 82 }; 83 84 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, 85 unsigned long offset) 86 { 87 return readl(padctl->regs.start + offset); 88 } 89 90 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, 91 u32 value, unsigned long offset) 92 { 93 writel(value, padctl->regs.start + offset); 94 } 95 96 extern struct tegra_xusb_padctl *padctl; 97 98 int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, 99 const void *fdt, int node); 100 int tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, 101 struct tegra_xusb_padctl_config *config); 102 103 #endif 104