1*1680d7b6SStephen Warren /* 2*1680d7b6SStephen Warren * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 3*1680d7b6SStephen Warren * 4*1680d7b6SStephen Warren * SPDX-License-Identifier: GPL-2.0 5*1680d7b6SStephen Warren */ 6*1680d7b6SStephen Warren 7*1680d7b6SStephen Warren #ifndef _TEGRA_XUSB_PADCTL_COMMON_H_ 8*1680d7b6SStephen Warren #define _TEGRA_XUSB_PADCTL_COMMON_H_ 9*1680d7b6SStephen Warren 10*1680d7b6SStephen Warren #include <common.h> 11*1680d7b6SStephen Warren #include <fdtdec.h> 12*1680d7b6SStephen Warren 13*1680d7b6SStephen Warren #include <asm/io.h> 14*1680d7b6SStephen Warren #include <asm/arch-tegra/xusb-padctl.h> 15*1680d7b6SStephen Warren 16*1680d7b6SStephen Warren struct tegra_xusb_padctl_lane { 17*1680d7b6SStephen Warren const char *name; 18*1680d7b6SStephen Warren 19*1680d7b6SStephen Warren unsigned int offset; 20*1680d7b6SStephen Warren unsigned int shift; 21*1680d7b6SStephen Warren unsigned int mask; 22*1680d7b6SStephen Warren unsigned int iddq; 23*1680d7b6SStephen Warren 24*1680d7b6SStephen Warren const unsigned int *funcs; 25*1680d7b6SStephen Warren unsigned int num_funcs; 26*1680d7b6SStephen Warren }; 27*1680d7b6SStephen Warren 28*1680d7b6SStephen Warren struct tegra_xusb_phy_ops { 29*1680d7b6SStephen Warren int (*prepare)(struct tegra_xusb_phy *phy); 30*1680d7b6SStephen Warren int (*enable)(struct tegra_xusb_phy *phy); 31*1680d7b6SStephen Warren int (*disable)(struct tegra_xusb_phy *phy); 32*1680d7b6SStephen Warren int (*unprepare)(struct tegra_xusb_phy *phy); 33*1680d7b6SStephen Warren }; 34*1680d7b6SStephen Warren 35*1680d7b6SStephen Warren struct tegra_xusb_phy { 36*1680d7b6SStephen Warren const struct tegra_xusb_phy_ops *ops; 37*1680d7b6SStephen Warren 38*1680d7b6SStephen Warren struct tegra_xusb_padctl *padctl; 39*1680d7b6SStephen Warren }; 40*1680d7b6SStephen Warren 41*1680d7b6SStephen Warren struct tegra_xusb_padctl_pin { 42*1680d7b6SStephen Warren const struct tegra_xusb_padctl_lane *lane; 43*1680d7b6SStephen Warren 44*1680d7b6SStephen Warren unsigned int func; 45*1680d7b6SStephen Warren int iddq; 46*1680d7b6SStephen Warren }; 47*1680d7b6SStephen Warren 48*1680d7b6SStephen Warren #define MAX_GROUPS 3 49*1680d7b6SStephen Warren #define MAX_PINS 6 50*1680d7b6SStephen Warren 51*1680d7b6SStephen Warren struct tegra_xusb_padctl_group { 52*1680d7b6SStephen Warren const char *name; 53*1680d7b6SStephen Warren 54*1680d7b6SStephen Warren const char *pins[MAX_PINS]; 55*1680d7b6SStephen Warren unsigned int num_pins; 56*1680d7b6SStephen Warren 57*1680d7b6SStephen Warren const char *func; 58*1680d7b6SStephen Warren int iddq; 59*1680d7b6SStephen Warren }; 60*1680d7b6SStephen Warren 61*1680d7b6SStephen Warren struct tegra_xusb_padctl_config { 62*1680d7b6SStephen Warren const char *name; 63*1680d7b6SStephen Warren 64*1680d7b6SStephen Warren struct tegra_xusb_padctl_group groups[MAX_GROUPS]; 65*1680d7b6SStephen Warren unsigned int num_groups; 66*1680d7b6SStephen Warren }; 67*1680d7b6SStephen Warren 68*1680d7b6SStephen Warren struct tegra_xusb_padctl { 69*1680d7b6SStephen Warren struct fdt_resource regs; 70*1680d7b6SStephen Warren 71*1680d7b6SStephen Warren unsigned int enable; 72*1680d7b6SStephen Warren 73*1680d7b6SStephen Warren struct tegra_xusb_phy phys[2]; 74*1680d7b6SStephen Warren 75*1680d7b6SStephen Warren const struct tegra_xusb_padctl_lane *lanes; 76*1680d7b6SStephen Warren unsigned int num_lanes; 77*1680d7b6SStephen Warren 78*1680d7b6SStephen Warren const char *const *functions; 79*1680d7b6SStephen Warren unsigned int num_functions; 80*1680d7b6SStephen Warren 81*1680d7b6SStephen Warren struct tegra_xusb_padctl_config config; 82*1680d7b6SStephen Warren }; 83*1680d7b6SStephen Warren 84*1680d7b6SStephen Warren static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, 85*1680d7b6SStephen Warren unsigned long offset) 86*1680d7b6SStephen Warren { 87*1680d7b6SStephen Warren return readl(padctl->regs.start + offset); 88*1680d7b6SStephen Warren } 89*1680d7b6SStephen Warren 90*1680d7b6SStephen Warren static inline void padctl_writel(struct tegra_xusb_padctl *padctl, 91*1680d7b6SStephen Warren u32 value, unsigned long offset) 92*1680d7b6SStephen Warren { 93*1680d7b6SStephen Warren writel(value, padctl->regs.start + offset); 94*1680d7b6SStephen Warren } 95*1680d7b6SStephen Warren 96*1680d7b6SStephen Warren extern struct tegra_xusb_padctl *padctl; 97*1680d7b6SStephen Warren 98*1680d7b6SStephen Warren int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, 99*1680d7b6SStephen Warren const void *fdt, int node); 100*1680d7b6SStephen Warren int tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, 101*1680d7b6SStephen Warren struct tegra_xusb_padctl_config *config); 102*1680d7b6SStephen Warren 103*1680d7b6SStephen Warren #endif 104