1*09f455dcSMasahiro Yamada /* 2*09f455dcSMasahiro Yamada * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 3*09f455dcSMasahiro Yamada * 4*09f455dcSMasahiro Yamada * This program is free software; you can redistribute it and/or modify it 5*09f455dcSMasahiro Yamada * under the terms and conditions of the GNU General Public License, 6*09f455dcSMasahiro Yamada * version 2, as published by the Free Software Foundation. 7*09f455dcSMasahiro Yamada * 8*09f455dcSMasahiro Yamada * This program is distributed in the hope it will be useful, but WITHOUT 9*09f455dcSMasahiro Yamada * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10*09f455dcSMasahiro Yamada * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11*09f455dcSMasahiro Yamada * more details. 12*09f455dcSMasahiro Yamada * 13*09f455dcSMasahiro Yamada * You should have received a copy of the GNU General Public License 14*09f455dcSMasahiro Yamada * along with this program. If not, see <http://www.gnu.org/licenses/>. 15*09f455dcSMasahiro Yamada */ 16*09f455dcSMasahiro Yamada 17*09f455dcSMasahiro Yamada #include <common.h> 18*09f455dcSMasahiro Yamada #include <asm/io.h> 19*09f455dcSMasahiro Yamada #include <asm/arch/tegra.h> 20*09f455dcSMasahiro Yamada #include <asm/arch-tegra/pmc.h> 21*09f455dcSMasahiro Yamada #include "../cpu.h" 22*09f455dcSMasahiro Yamada 23*09f455dcSMasahiro Yamada static void enable_cpu_power_rail(void) 24*09f455dcSMasahiro Yamada { 25*09f455dcSMasahiro Yamada struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 26*09f455dcSMasahiro Yamada u32 reg; 27*09f455dcSMasahiro Yamada 28*09f455dcSMasahiro Yamada reg = readl(&pmc->pmc_cntrl); 29*09f455dcSMasahiro Yamada reg |= CPUPWRREQ_OE; 30*09f455dcSMasahiro Yamada writel(reg, &pmc->pmc_cntrl); 31*09f455dcSMasahiro Yamada 32*09f455dcSMasahiro Yamada /* 33*09f455dcSMasahiro Yamada * The TI PMU65861C needs a 3.75ms delay between enabling 34*09f455dcSMasahiro Yamada * the power rail and enabling the CPU clock. This delay 35*09f455dcSMasahiro Yamada * between SM1EN and SM1 is for switching time + the ramp 36*09f455dcSMasahiro Yamada * up of the voltage to the CPU (VDD_CPU from PMU). 37*09f455dcSMasahiro Yamada */ 38*09f455dcSMasahiro Yamada udelay(3750); 39*09f455dcSMasahiro Yamada } 40*09f455dcSMasahiro Yamada 41*09f455dcSMasahiro Yamada void start_cpu(u32 reset_vector) 42*09f455dcSMasahiro Yamada { 43*09f455dcSMasahiro Yamada /* Enable VDD_CPU */ 44*09f455dcSMasahiro Yamada enable_cpu_power_rail(); 45*09f455dcSMasahiro Yamada 46*09f455dcSMasahiro Yamada /* Hold the CPUs in reset */ 47*09f455dcSMasahiro Yamada reset_A9_cpu(1); 48*09f455dcSMasahiro Yamada 49*09f455dcSMasahiro Yamada /* Disable the CPU clock */ 50*09f455dcSMasahiro Yamada enable_cpu_clock(0); 51*09f455dcSMasahiro Yamada 52*09f455dcSMasahiro Yamada /* Enable CoreSight */ 53*09f455dcSMasahiro Yamada clock_enable_coresight(1); 54*09f455dcSMasahiro Yamada 55*09f455dcSMasahiro Yamada /* 56*09f455dcSMasahiro Yamada * Set the entry point for CPU execution from reset, 57*09f455dcSMasahiro Yamada * if it's a non-zero value. 58*09f455dcSMasahiro Yamada */ 59*09f455dcSMasahiro Yamada if (reset_vector) 60*09f455dcSMasahiro Yamada writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 61*09f455dcSMasahiro Yamada 62*09f455dcSMasahiro Yamada /* Enable the CPU clock */ 63*09f455dcSMasahiro Yamada enable_cpu_clock(1); 64*09f455dcSMasahiro Yamada 65*09f455dcSMasahiro Yamada /* If the CPU doesn't already have power, power it up */ 66*09f455dcSMasahiro Yamada powerup_cpu(); 67*09f455dcSMasahiro Yamada 68*09f455dcSMasahiro Yamada /* Take the CPU out of reset */ 69*09f455dcSMasahiro Yamada reset_A9_cpu(0); 70*09f455dcSMasahiro Yamada } 71