109f455dcSMasahiro Yamada /* 209f455dcSMasahiro Yamada * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 309f455dcSMasahiro Yamada * 4*5b8031ccSTom Rini * SPDX-License-Identifier: GPL-2.0 509f455dcSMasahiro Yamada */ 609f455dcSMasahiro Yamada 709f455dcSMasahiro Yamada #include <common.h> 809f455dcSMasahiro Yamada #include <asm/io.h> 909f455dcSMasahiro Yamada #include <asm/arch/tegra.h> 1009f455dcSMasahiro Yamada #include <asm/arch-tegra/pmc.h> 1109f455dcSMasahiro Yamada #include "../cpu.h" 1209f455dcSMasahiro Yamada enable_cpu_power_rail(void)1309f455dcSMasahiro Yamadastatic void enable_cpu_power_rail(void) 1409f455dcSMasahiro Yamada { 1509f455dcSMasahiro Yamada struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 1609f455dcSMasahiro Yamada u32 reg; 1709f455dcSMasahiro Yamada 1809f455dcSMasahiro Yamada reg = readl(&pmc->pmc_cntrl); 1909f455dcSMasahiro Yamada reg |= CPUPWRREQ_OE; 2009f455dcSMasahiro Yamada writel(reg, &pmc->pmc_cntrl); 2109f455dcSMasahiro Yamada 2209f455dcSMasahiro Yamada /* 2309f455dcSMasahiro Yamada * The TI PMU65861C needs a 3.75ms delay between enabling 2409f455dcSMasahiro Yamada * the power rail and enabling the CPU clock. This delay 2509f455dcSMasahiro Yamada * between SM1EN and SM1 is for switching time + the ramp 2609f455dcSMasahiro Yamada * up of the voltage to the CPU (VDD_CPU from PMU). 2709f455dcSMasahiro Yamada */ 2809f455dcSMasahiro Yamada udelay(3750); 2909f455dcSMasahiro Yamada } 3009f455dcSMasahiro Yamada start_cpu(u32 reset_vector)3109f455dcSMasahiro Yamadavoid start_cpu(u32 reset_vector) 3209f455dcSMasahiro Yamada { 3309f455dcSMasahiro Yamada /* Enable VDD_CPU */ 3409f455dcSMasahiro Yamada enable_cpu_power_rail(); 3509f455dcSMasahiro Yamada 3609f455dcSMasahiro Yamada /* Hold the CPUs in reset */ 3709f455dcSMasahiro Yamada reset_A9_cpu(1); 3809f455dcSMasahiro Yamada 3909f455dcSMasahiro Yamada /* Disable the CPU clock */ 4009f455dcSMasahiro Yamada enable_cpu_clock(0); 4109f455dcSMasahiro Yamada 4209f455dcSMasahiro Yamada /* Enable CoreSight */ 4309f455dcSMasahiro Yamada clock_enable_coresight(1); 4409f455dcSMasahiro Yamada 4509f455dcSMasahiro Yamada /* 4609f455dcSMasahiro Yamada * Set the entry point for CPU execution from reset, 4709f455dcSMasahiro Yamada * if it's a non-zero value. 4809f455dcSMasahiro Yamada */ 4909f455dcSMasahiro Yamada if (reset_vector) 5009f455dcSMasahiro Yamada writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 5109f455dcSMasahiro Yamada 5209f455dcSMasahiro Yamada /* Enable the CPU clock */ 5309f455dcSMasahiro Yamada enable_cpu_clock(1); 5409f455dcSMasahiro Yamada 5509f455dcSMasahiro Yamada /* If the CPU doesn't already have power, power it up */ 5609f455dcSMasahiro Yamada powerup_cpu(); 5709f455dcSMasahiro Yamada 5809f455dcSMasahiro Yamada /* Take the CPU out of reset */ 5909f455dcSMasahiro Yamada reset_A9_cpu(0); 6009f455dcSMasahiro Yamada } 61