12a5f7f20SStephen Warren /*
22a5f7f20SStephen Warren * Copyright (c) 2016, NVIDIA CORPORATION.
32a5f7f20SStephen Warren *
42a5f7f20SStephen Warren * SPDX-License-Identifier: GPL-2.0+
52a5f7f20SStephen Warren */
62a5f7f20SStephen Warren
72a5f7f20SStephen Warren #include <common.h>
82a5f7f20SStephen Warren #include <fdt_support.h>
92a5f7f20SStephen Warren #include <fdtdec.h>
102a5f7f20SStephen Warren #include <asm/arch/tegra.h>
112a5f7f20SStephen Warren
122a5f7f20SStephen Warren DECLARE_GLOBAL_DATA_PTR;
132a5f7f20SStephen Warren
142a5f7f20SStephen Warren extern unsigned long nvtboot_boot_x0;
152a5f7f20SStephen Warren
162a5f7f20SStephen Warren /*
172a5f7f20SStephen Warren * A parsed version of /memory/reg from the DTB that is passed to U-Boot in x0.
182a5f7f20SStephen Warren *
192a5f7f20SStephen Warren * We only support up to two banks since that's all the binary bootloader
202a5f7f20SStephen Warren * ever sets. We assume bank 0 is RAM below 4G and bank 1 is RAM above 4G.
212a5f7f20SStephen Warren * This is all a fairly safe assumption, since the L4T kernel makes the same
222a5f7f20SStephen Warren * assumptions, so the bootloader is unlikely to change.
232a5f7f20SStephen Warren *
242a5f7f20SStephen Warren * This is written to before relocation, and hence cannot be in .bss, since
252a5f7f20SStephen Warren * .bss overlaps the DTB that's appended to the U-Boot binary. The initializer
262a5f7f20SStephen Warren * forces this into .data and avoids this issue. This also has the nice side-
272a5f7f20SStephen Warren * effect of the content being valid after relocation.
282a5f7f20SStephen Warren */
292a5f7f20SStephen Warren static struct {
302a5f7f20SStephen Warren u64 start;
312a5f7f20SStephen Warren u64 size;
322a5f7f20SStephen Warren } ram_banks[2] = {{1}};
332a5f7f20SStephen Warren
dram_init(void)342a5f7f20SStephen Warren int dram_init(void)
352a5f7f20SStephen Warren {
362a5f7f20SStephen Warren unsigned int na, ns;
372a5f7f20SStephen Warren const void *nvtboot_blob = (void *)nvtboot_boot_x0;
382a5f7f20SStephen Warren int node, len, i;
392a5f7f20SStephen Warren const u32 *prop;
402a5f7f20SStephen Warren
412a5f7f20SStephen Warren memset(ram_banks, 0, sizeof(ram_banks));
422a5f7f20SStephen Warren
432a5f7f20SStephen Warren na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2);
442a5f7f20SStephen Warren ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2);
452a5f7f20SStephen Warren
462a5f7f20SStephen Warren node = fdt_path_offset(nvtboot_blob, "/memory");
472a5f7f20SStephen Warren if (node < 0) {
48*90aa625cSMasahiro Yamada pr_err("Can't find /memory node in nvtboot DTB");
492a5f7f20SStephen Warren hang();
502a5f7f20SStephen Warren }
512a5f7f20SStephen Warren prop = fdt_getprop(nvtboot_blob, node, "reg", &len);
522a5f7f20SStephen Warren if (!prop) {
53*90aa625cSMasahiro Yamada pr_err("Can't find /memory/reg property in nvtboot DTB");
542a5f7f20SStephen Warren hang();
552a5f7f20SStephen Warren }
562a5f7f20SStephen Warren
572a5f7f20SStephen Warren len /= (na + ns);
582a5f7f20SStephen Warren if (len > ARRAY_SIZE(ram_banks))
592a5f7f20SStephen Warren len = ARRAY_SIZE(ram_banks);
602a5f7f20SStephen Warren
612a5f7f20SStephen Warren gd->ram_size = 0;
622a5f7f20SStephen Warren for (i = 0; i < len; i++) {
63eed36609SSimon Glass ram_banks[i].start = fdt_read_number(prop, na);
642a5f7f20SStephen Warren prop += na;
65eed36609SSimon Glass ram_banks[i].size = fdt_read_number(prop, ns);
662a5f7f20SStephen Warren prop += ns;
672a5f7f20SStephen Warren gd->ram_size += ram_banks[i].size;
682a5f7f20SStephen Warren }
692a5f7f20SStephen Warren
702a5f7f20SStephen Warren return 0;
712a5f7f20SStephen Warren }
722a5f7f20SStephen Warren
732a5f7f20SStephen Warren extern unsigned long nvtboot_boot_x0;
742a5f7f20SStephen Warren
dram_init_banksize(void)7576b00acaSSimon Glass int dram_init_banksize(void)
762a5f7f20SStephen Warren {
772a5f7f20SStephen Warren int i;
782a5f7f20SStephen Warren
792a5f7f20SStephen Warren for (i = 0; i < 2; i++) {
802a5f7f20SStephen Warren gd->bd->bi_dram[i].start = ram_banks[i].start;
812a5f7f20SStephen Warren gd->bd->bi_dram[i].size = ram_banks[i].size;
822a5f7f20SStephen Warren }
8376b00acaSSimon Glass
8476b00acaSSimon Glass return 0;
852a5f7f20SStephen Warren }
862a5f7f20SStephen Warren
board_get_usable_ram_top(ulong total_size)872a5f7f20SStephen Warren ulong board_get_usable_ram_top(ulong total_size)
882a5f7f20SStephen Warren {
892a5f7f20SStephen Warren return ram_banks[0].start + ram_banks[0].size;
902a5f7f20SStephen Warren }
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