1b9ae6415SStephen Warren/* 2b9ae6415SStephen Warren * Copyright (c) 2016, NVIDIA CORPORATION. 3b9ae6415SStephen Warren * 4b9ae6415SStephen Warren * SPDX-License-Identifier: GPL-2.0 5b9ae6415SStephen Warren */ 6b9ae6415SStephen Warren 7b9ae6415SStephen Warren#include <config.h> 8b9ae6415SStephen Warren#include <linux/linkage.h> 9b9ae6415SStephen Warren 10b9ae6415SStephen Warren#define SMC_SIP_INVOKE_MCE 0x82FFFF00 11b9ae6415SStephen Warren#define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11) 12*a8d05261SStephen Warren#define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14) 13*a8d05261SStephen Warren#define MCE_SMC_ROC_CLEAN_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 15) 14b9ae6415SStephen Warren 15*a8d05261SStephen WarrenENTRY(__asm_tegra_cache_smc) 16b9ae6415SStephen Warren mov x1, #0 17b9ae6415SStephen Warren mov x2, #0 18b9ae6415SStephen Warren mov x3, #0 19b9ae6415SStephen Warren mov x4, #0 20b9ae6415SStephen Warren mov x5, #0 21b9ae6415SStephen Warren mov x6, #0 22b9ae6415SStephen Warren smc #0 23b9ae6415SStephen Warren mov x0, #0 24b9ae6415SStephen Warren ret 25*a8d05261SStephen WarrenENDPROC(__asm_invalidate_l3_dcache) 26*a8d05261SStephen Warren 27*a8d05261SStephen WarrenENTRY(__asm_invalidate_l3_dcache) 28*a8d05261SStephen Warren mov x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff) 29*a8d05261SStephen Warren movk x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16 30*a8d05261SStephen Warren b __asm_tegra_cache_smc 31*a8d05261SStephen WarrenENDPROC(__asm_invalidate_l3_dcache) 32*a8d05261SStephen Warren 33*a8d05261SStephen WarrenENTRY(__asm_flush_l3_dcache) 34*a8d05261SStephen Warren mov x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff) 35*a8d05261SStephen Warren movk x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16 36*a8d05261SStephen Warren b __asm_tegra_cache_smc 371ab557a0SStephen WarrenENDPROC(__asm_flush_l3_dcache) 38*a8d05261SStephen Warren 39*a8d05261SStephen WarrenENTRY(__asm_invalidate_l3_icache) 40*a8d05261SStephen Warren mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff) 41*a8d05261SStephen Warren movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16 42*a8d05261SStephen Warren b __asm_tegra_cache_smc 43*a8d05261SStephen WarrenENDPROC(__asm_invalidate_l3_icache) 44