1 /* 2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt 8 9 #include <common.h> 10 #include <errno.h> 11 #include <fdtdec.h> 12 #include <malloc.h> 13 14 #include "../xusb-padctl-common.h" 15 16 #include <asm/io.h> 17 18 #include <asm/arch/clock.h> 19 #include <asm/arch-tegra/xusb-padctl.h> 20 21 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 22 23 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c 24 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) 25 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25) 26 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24) 27 28 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040 29 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19) 30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12) 31 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) 32 33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044 34 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6) 35 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5) 36 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4) 37 38 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138 39 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27) 40 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24) 41 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3) 42 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1) 43 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0) 44 45 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148 46 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1) 47 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0) 48 49 enum tegra124_function { 50 TEGRA124_FUNC_SNPS, 51 TEGRA124_FUNC_XUSB, 52 TEGRA124_FUNC_UART, 53 TEGRA124_FUNC_PCIE, 54 TEGRA124_FUNC_USB3, 55 TEGRA124_FUNC_SATA, 56 TEGRA124_FUNC_RSVD, 57 }; 58 59 static const char *const tegra124_functions[] = { 60 "snps", 61 "xusb", 62 "uart", 63 "pcie", 64 "usb3", 65 "sata", 66 "rsvd", 67 }; 68 69 static const unsigned int tegra124_otg_functions[] = { 70 TEGRA124_FUNC_SNPS, 71 TEGRA124_FUNC_XUSB, 72 TEGRA124_FUNC_UART, 73 TEGRA124_FUNC_RSVD, 74 }; 75 76 static const unsigned int tegra124_usb_functions[] = { 77 TEGRA124_FUNC_SNPS, 78 TEGRA124_FUNC_XUSB, 79 }; 80 81 static const unsigned int tegra124_pci_functions[] = { 82 TEGRA124_FUNC_PCIE, 83 TEGRA124_FUNC_USB3, 84 TEGRA124_FUNC_SATA, 85 TEGRA124_FUNC_RSVD, 86 }; 87 88 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ 89 { \ 90 .name = _name, \ 91 .offset = _offset, \ 92 .shift = _shift, \ 93 .mask = _mask, \ 94 .iddq = _iddq, \ 95 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \ 96 .funcs = tegra124_##_funcs##_functions, \ 97 } 98 99 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = { 100 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg), 101 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg), 102 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg), 103 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb), 104 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb), 105 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb), 106 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci), 107 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci), 108 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci), 109 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci), 110 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci), 111 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci), 112 }; 113 114 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) 115 { 116 u32 value; 117 118 if (padctl->enable++ > 0) 119 return 0; 120 121 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 122 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 123 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 124 125 udelay(100); 126 127 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 128 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 129 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 130 131 udelay(100); 132 133 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 134 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 135 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 136 137 return 0; 138 } 139 140 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) 141 { 142 u32 value; 143 144 if (padctl->enable == 0) { 145 error("unbalanced enable/disable"); 146 return 0; 147 } 148 149 if (--padctl->enable > 0) 150 return 0; 151 152 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 153 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 154 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 155 156 udelay(100); 157 158 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 159 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 160 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 161 162 udelay(100); 163 164 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 165 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 166 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 167 168 return 0; 169 } 170 171 static int phy_prepare(struct tegra_xusb_phy *phy) 172 { 173 return tegra_xusb_padctl_enable(phy->padctl); 174 } 175 176 static int phy_unprepare(struct tegra_xusb_phy *phy) 177 { 178 return tegra_xusb_padctl_disable(phy->padctl); 179 } 180 181 static int pcie_phy_enable(struct tegra_xusb_phy *phy) 182 { 183 struct tegra_xusb_padctl *padctl = phy->padctl; 184 int err = -ETIMEDOUT; 185 unsigned long start; 186 u32 value; 187 188 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 189 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK; 190 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 191 192 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); 193 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN | 194 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN | 195 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL; 196 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); 197 198 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 199 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; 200 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 201 202 start = get_timer(0); 203 204 while (get_timer(start) < 50) { 205 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 206 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) { 207 err = 0; 208 break; 209 } 210 } 211 212 return err; 213 } 214 215 static int pcie_phy_disable(struct tegra_xusb_phy *phy) 216 { 217 struct tegra_xusb_padctl *padctl = phy->padctl; 218 u32 value; 219 220 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 221 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; 222 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 223 224 return 0; 225 } 226 227 static int sata_phy_enable(struct tegra_xusb_phy *phy) 228 { 229 struct tegra_xusb_padctl *padctl = phy->padctl; 230 int err = -ETIMEDOUT; 231 unsigned long start; 232 u32 value; 233 234 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 235 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 236 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; 237 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 238 239 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 240 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 241 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; 242 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 243 244 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 245 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; 246 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 247 248 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 249 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; 250 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 251 252 start = get_timer(0); 253 254 while (get_timer(start) < 50) { 255 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 256 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) { 257 err = 0; 258 break; 259 } 260 } 261 262 return err; 263 } 264 265 static int sata_phy_disable(struct tegra_xusb_phy *phy) 266 { 267 struct tegra_xusb_padctl *padctl = phy->padctl; 268 u32 value; 269 270 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 271 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; 272 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 273 274 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 275 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; 276 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 277 278 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 279 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 280 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; 281 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 282 283 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 284 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 285 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; 286 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 287 288 return 0; 289 } 290 291 static const struct tegra_xusb_phy_ops pcie_phy_ops = { 292 .prepare = phy_prepare, 293 .enable = pcie_phy_enable, 294 .disable = pcie_phy_disable, 295 .unprepare = phy_unprepare, 296 }; 297 298 static const struct tegra_xusb_phy_ops sata_phy_ops = { 299 .prepare = phy_prepare, 300 .enable = sata_phy_enable, 301 .disable = sata_phy_disable, 302 .unprepare = phy_unprepare, 303 }; 304 305 struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) { 306 .phys = { 307 [0] = { 308 .ops = &pcie_phy_ops, 309 }, 310 [1] = { 311 .ops = &sata_phy_ops, 312 }, 313 }, 314 }; 315 316 int process_nodes(const void *fdt, int nodes[], unsigned int count) 317 { 318 unsigned int i; 319 320 for (i = 0; i < count; i++) { 321 enum fdt_compat_id id; 322 int err; 323 324 if (!fdtdec_get_is_enabled(fdt, nodes[i])) 325 continue; 326 327 id = fdtdec_lookup(fdt, nodes[i]); 328 switch (id) { 329 case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL: 330 break; 331 332 default: 333 error("unsupported compatible: %s", 334 fdtdec_get_compatible(id)); 335 continue; 336 } 337 338 padctl->num_lanes = ARRAY_SIZE(tegra124_lanes); 339 padctl->lanes = tegra124_lanes; 340 341 padctl->num_functions = ARRAY_SIZE(tegra124_functions); 342 padctl->functions = tegra124_functions; 343 344 err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]); 345 if (err < 0) { 346 error("failed to parse DT: %d", err); 347 continue; 348 } 349 350 /* deassert XUSB padctl reset */ 351 reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0); 352 353 err = tegra_xusb_padctl_config_apply(padctl, &padctl->config); 354 if (err < 0) { 355 error("failed to apply pinmux: %d", err); 356 continue; 357 } 358 359 /* only a single instance is supported */ 360 break; 361 } 362 363 return 0; 364 } 365 366 void tegra_xusb_padctl_init(const void *fdt) 367 { 368 int count, nodes[1]; 369 370 count = fdtdec_find_aliases_for_id(fdt, "padctl", 371 COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, 372 nodes, ARRAY_SIZE(nodes)); 373 if (process_nodes(fdt, nodes, count)) 374 return; 375 } 376