1*237c3637SMasahiro Yamada /* 2*237c3637SMasahiro Yamada * Copyright (c) 2011 The Chromium OS Authors. 3*237c3637SMasahiro Yamada * 4*237c3637SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 5*237c3637SMasahiro Yamada */ 6*237c3637SMasahiro Yamada 7*237c3637SMasahiro Yamada #include <common.h> 8*237c3637SMasahiro Yamada #include "emc.h" 9*237c3637SMasahiro Yamada #include <asm/io.h> 10*237c3637SMasahiro Yamada #include <asm/arch/clock.h> 11*237c3637SMasahiro Yamada #include <asm/arch/emc.h> 12*237c3637SMasahiro Yamada #include <asm/arch/pmu.h> 13*237c3637SMasahiro Yamada #include <asm/arch/tegra.h> 14*237c3637SMasahiro Yamada #include <asm/arch-tegra/ap.h> 15*237c3637SMasahiro Yamada #include <asm/arch-tegra/clk_rst.h> 16*237c3637SMasahiro Yamada #include <asm/arch-tegra/sys_proto.h> 17*237c3637SMasahiro Yamada 18*237c3637SMasahiro Yamada DECLARE_GLOBAL_DATA_PTR; 19*237c3637SMasahiro Yamada 20*237c3637SMasahiro Yamada /* These rates are hard-coded for now, until fdt provides them */ 21*237c3637SMasahiro Yamada #define EMC_SDRAM_RATE_T20 (333000 * 2 * 1000) 22*237c3637SMasahiro Yamada #define EMC_SDRAM_RATE_T25 (380000 * 2 * 1000) 23*237c3637SMasahiro Yamada board_emc_init(void)24*237c3637SMasahiro Yamadaint board_emc_init(void) 25*237c3637SMasahiro Yamada { 26*237c3637SMasahiro Yamada unsigned rate; 27*237c3637SMasahiro Yamada 28*237c3637SMasahiro Yamada switch (tegra_get_chip_sku()) { 29*237c3637SMasahiro Yamada default: 30*237c3637SMasahiro Yamada case TEGRA_SOC_T20: 31*237c3637SMasahiro Yamada rate = EMC_SDRAM_RATE_T20; 32*237c3637SMasahiro Yamada break; 33*237c3637SMasahiro Yamada case TEGRA_SOC_T25: 34*237c3637SMasahiro Yamada rate = EMC_SDRAM_RATE_T25; 35*237c3637SMasahiro Yamada break; 36*237c3637SMasahiro Yamada } 37*237c3637SMasahiro Yamada return tegra_set_emc(gd->fdt_blob, rate); 38*237c3637SMasahiro Yamada } 39