1 /* 2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 /* Tegra SoC common clock control functions */ 18 19 #include <common.h> 20 #include <errno.h> 21 #include <asm/io.h> 22 #include <asm/arch/clock.h> 23 #include <asm/arch/tegra.h> 24 #include <asm/arch-tegra/ap.h> 25 #include <asm/arch-tegra/clk_rst.h> 26 #include <asm/arch-tegra/pmc.h> 27 #include <asm/arch-tegra/timer.h> 28 #include <div64.h> 29 #include <fdtdec.h> 30 31 /* 32 * This is our record of the current clock rate of each clock. We don't 33 * fill all of these in since we are only really interested in clocks which 34 * we use as parents. 35 */ 36 static unsigned pll_rate[CLOCK_ID_COUNT]; 37 38 /* 39 * The oscillator frequency is fixed to one of four set values. Based on this 40 * the other clocks are set up appropriately. 41 */ 42 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = { 43 13000000, 44 19200000, 45 12000000, 46 26000000, 47 38400000, 48 48000000, 49 }; 50 51 /* return 1 if a peripheral ID is in range */ 52 #define clock_type_id_isvalid(id) ((id) >= 0 && \ 53 (id) < CLOCK_TYPE_COUNT) 54 55 char pllp_valid = 1; /* PLLP is set up correctly */ 56 57 /* return 1 if a periphc_internal_id is in range */ 58 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \ 59 (id) < PERIPHC_COUNT) 60 61 /* number of clock outputs of a PLL */ 62 static const u8 pll_num_clkouts[] = { 63 1, /* PLLC */ 64 1, /* PLLM */ 65 4, /* PLLP */ 66 1, /* PLLA */ 67 0, /* PLLU */ 68 0, /* PLLD */ 69 }; 70 71 int clock_get_osc_bypass(void) 72 { 73 struct clk_rst_ctlr *clkrst = 74 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 75 u32 reg; 76 77 reg = readl(&clkrst->crc_osc_ctrl); 78 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT; 79 } 80 81 /* Returns a pointer to the registers of the given pll */ 82 static struct clk_pll *get_pll(enum clock_id clkid) 83 { 84 struct clk_rst_ctlr *clkrst = 85 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 86 87 assert(clock_id_is_pll(clkid)); 88 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) { 89 debug("%s: Invalid PLL %d\n", __func__, clkid); 90 return NULL; 91 } 92 return &clkrst->crc_pll[clkid]; 93 } 94 95 __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) 96 { 97 return NULL; 98 } 99 100 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, 101 u32 *divp, u32 *cpcon, u32 *lfcon) 102 { 103 struct clk_pll *pll = get_pll(clkid); 104 u32 data; 105 106 assert(clkid != CLOCK_ID_USB); 107 108 /* Safety check, adds to code size but is small */ 109 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB) 110 return -1; 111 data = readl(&pll->pll_base); 112 *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT; 113 *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT; 114 *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT; 115 data = readl(&pll->pll_misc); 116 *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT; 117 *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT; 118 #if defined(CONFIG_TEGRA210) 119 /* T210 PLLU uses KCP/KVCO instead of CPCON/LFCON */ 120 *cpcon = (data & PLLU_KCP_MASK) >> PLLU_KCP_SHIFT; 121 *lfcon = (data & PLLU_KVCO_MASK) >> PLLU_KVCO_SHIFT; 122 #endif 123 return 0; 124 } 125 126 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, 127 u32 divp, u32 cpcon, u32 lfcon) 128 { 129 struct clk_pll *pll = NULL; 130 u32 misc_data, data; 131 132 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) 133 pll = get_pll(clkid); 134 135 /* 136 * We cheat by treating all PLL (except PLLU) in the same fashion. 137 * This works only because: 138 * - same fields are always mapped at same offsets, except DCCON 139 * - DCCON is always 0, doesn't conflict 140 * - M,N, P of PLLP values are ignored for PLLP 141 * NOTE: Above is no longer true with T210 - TBD: FIX THIS 142 */ 143 misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT); 144 145 #if defined(CONFIG_TEGRA210) 146 /* T210 PLLU uses KCP/KVCO instead of cpcon/lfcon */ 147 if (clkid == CLOCK_ID_USB) { 148 /* preserve EN_LOCKDET, set by default */ 149 misc_data = readl(&pll->pll_misc); 150 misc_data |= (cpcon << PLLU_KCP_SHIFT) | 151 (lfcon << PLLU_KVCO_SHIFT); 152 } 153 #endif 154 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) | 155 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT); 156 157 if (clkid == CLOCK_ID_USB) 158 #if defined(CONFIG_TEGRA210) 159 data |= divp << PLLU_DIVP_SHIFT; 160 #else 161 data |= divp << PLLU_VCO_FREQ_SHIFT; 162 #endif 163 else 164 data |= divp << PLL_DIVP_SHIFT; 165 if (pll) { 166 writel(misc_data, &pll->pll_misc); 167 writel(data, &pll->pll_base); 168 } else { 169 struct clk_pll_simple *pll = clock_get_simple_pll(clkid); 170 171 if (!pll) { 172 debug("%s: Uknown simple PLL %d\n", __func__, clkid); 173 return 0; 174 } 175 writel(misc_data, &pll->pll_misc); 176 writel(data, &pll->pll_base); 177 } 178 179 /* calculate the stable time */ 180 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US; 181 } 182 183 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, 184 unsigned divisor) 185 { 186 u32 *reg = get_periph_source_reg(periph_id); 187 u32 value; 188 189 value = readl(reg); 190 191 value &= ~OUT_CLK_SOURCE_31_30_MASK; 192 value |= source << OUT_CLK_SOURCE_31_30_SHIFT; 193 194 value &= ~OUT_CLK_DIVISOR_MASK; 195 value |= divisor << OUT_CLK_DIVISOR_SHIFT; 196 197 writel(value, reg); 198 } 199 200 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, 201 unsigned source) 202 { 203 u32 *reg = get_periph_source_reg(periph_id); 204 205 switch (mux_bits) { 206 case MASK_BITS_31_30: 207 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, 208 source << OUT_CLK_SOURCE_31_30_SHIFT); 209 break; 210 211 case MASK_BITS_31_29: 212 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK, 213 source << OUT_CLK_SOURCE_31_29_SHIFT); 214 break; 215 216 case MASK_BITS_31_28: 217 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, 218 source << OUT_CLK_SOURCE_31_28_SHIFT); 219 break; 220 221 default: 222 return -1; 223 } 224 225 return 0; 226 } 227 228 void clock_ll_set_source(enum periph_id periph_id, unsigned source) 229 { 230 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source); 231 } 232 233 /** 234 * Given the parent's rate and the required rate for the children, this works 235 * out the peripheral clock divider to use, in 7.1 binary format. 236 * 237 * @param divider_bits number of divider bits (8 or 16) 238 * @param parent_rate clock rate of parent clock in Hz 239 * @param rate required clock rate for this clock 240 * @return divider which should be used 241 */ 242 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate, 243 unsigned long rate) 244 { 245 u64 divider = parent_rate * 2; 246 unsigned max_divider = 1 << divider_bits; 247 248 divider += rate - 1; 249 do_div(divider, rate); 250 251 if ((s64)divider - 2 < 0) 252 return 0; 253 254 if ((s64)divider - 2 >= max_divider) 255 return -1; 256 257 return divider - 2; 258 } 259 260 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate) 261 { 262 struct clk_pll *pll = get_pll(clkid); 263 int data = 0, div = 0, offset = 0; 264 265 if (!clock_id_is_pll(clkid)) 266 return -1; 267 268 if (pllout + 1 > pll_num_clkouts[clkid]) 269 return -1; 270 271 div = clk_get_divider(8, pll_rate[clkid], rate); 272 273 if (div < 0) 274 return -1; 275 276 /* out2 and out4 are in the high part of the register */ 277 if (pllout == PLL_OUT2 || pllout == PLL_OUT4) 278 offset = 16; 279 280 data = (div << PLL_OUT_RATIO_SHIFT) | 281 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN; 282 clrsetbits_le32(&pll->pll_out[pllout >> 1], 283 PLL_OUT_RATIO_MASK << offset, data << offset); 284 285 return 0; 286 } 287 288 /** 289 * Given the parent's rate and the divider in 7.1 format, this works out the 290 * resulting peripheral clock rate. 291 * 292 * @param parent_rate clock rate of parent clock in Hz 293 * @param divider which should be used in 7.1 format 294 * @return effective clock rate of peripheral 295 */ 296 static unsigned long get_rate_from_divider(unsigned long parent_rate, 297 int divider) 298 { 299 u64 rate; 300 301 rate = (u64)parent_rate * 2; 302 do_div(rate, divider + 2); 303 return rate; 304 } 305 306 unsigned long clock_get_periph_rate(enum periph_id periph_id, 307 enum clock_id parent) 308 { 309 u32 *reg = get_periph_source_reg(periph_id); 310 311 return get_rate_from_divider(pll_rate[parent], 312 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT); 313 } 314 315 /** 316 * Find the best available 7.1 format divisor given a parent clock rate and 317 * required child clock rate. This function assumes that a second-stage 318 * divisor is available which can divide by powers of 2 from 1 to 256. 319 * 320 * @param divider_bits number of divider bits (8 or 16) 321 * @param parent_rate clock rate of parent clock in Hz 322 * @param rate required clock rate for this clock 323 * @param extra_div value for the second-stage divisor (not set if this 324 * function returns -1. 325 * @return divider which should be used, or -1 if nothing is valid 326 * 327 */ 328 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, 329 unsigned long rate, int *extra_div) 330 { 331 int shift; 332 int best_divider = -1; 333 int best_error = rate; 334 335 /* try dividers from 1 to 256 and find closest match */ 336 for (shift = 0; shift <= 8 && best_error > 0; shift++) { 337 unsigned divided_parent = parent_rate >> shift; 338 int divider = clk_get_divider(divider_bits, divided_parent, 339 rate); 340 unsigned effective_rate = get_rate_from_divider(divided_parent, 341 divider); 342 int error = rate - effective_rate; 343 344 /* Given a valid divider, look for the lowest error */ 345 if (divider != -1 && error < best_error) { 346 best_error = error; 347 *extra_div = 1 << shift; 348 best_divider = divider; 349 } 350 } 351 352 /* return what we found - *extra_div will already be set */ 353 return best_divider; 354 } 355 356 /** 357 * Adjust peripheral PLL to use the given divider and source. 358 * 359 * @param periph_id peripheral to adjust 360 * @param source Source number (0-3 or 0-7) 361 * @param mux_bits Number of mux bits (2 or 4) 362 * @param divider Required divider in 7.1 or 15.1 format 363 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid 364 * for this peripheral) 365 */ 366 static int adjust_periph_pll(enum periph_id periph_id, int source, 367 int mux_bits, unsigned divider) 368 { 369 u32 *reg = get_periph_source_reg(periph_id); 370 371 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK, 372 divider << OUT_CLK_DIVISOR_SHIFT); 373 udelay(1); 374 375 /* work out the source clock and set it */ 376 if (source < 0) 377 return -1; 378 379 clock_ll_set_source_bits(periph_id, mux_bits, source); 380 381 udelay(2); 382 return 0; 383 } 384 385 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, 386 enum clock_id parent, unsigned rate, int *extra_div) 387 { 388 unsigned effective_rate; 389 int mux_bits, divider_bits, source; 390 int divider; 391 int xdiv = 0; 392 393 /* work out the source clock and set it */ 394 source = get_periph_clock_source(periph_id, parent, &mux_bits, 395 ÷r_bits); 396 397 divider = find_best_divider(divider_bits, pll_rate[parent], 398 rate, &xdiv); 399 if (extra_div) 400 *extra_div = xdiv; 401 402 assert(divider >= 0); 403 if (adjust_periph_pll(periph_id, source, mux_bits, divider)) 404 return -1U; 405 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate, 406 get_periph_source_reg(periph_id), 407 readl(get_periph_source_reg(periph_id))); 408 409 /* Check what we ended up with. This shouldn't matter though */ 410 effective_rate = clock_get_periph_rate(periph_id, parent); 411 if (extra_div) 412 effective_rate /= *extra_div; 413 if (rate != effective_rate) 414 debug("Requested clock rate %u not honored (got %u)\n", 415 rate, effective_rate); 416 return effective_rate; 417 } 418 419 unsigned clock_start_periph_pll(enum periph_id periph_id, 420 enum clock_id parent, unsigned rate) 421 { 422 unsigned effective_rate; 423 424 reset_set_enable(periph_id, 1); 425 clock_enable(periph_id); 426 427 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate, 428 NULL); 429 430 reset_set_enable(periph_id, 0); 431 return effective_rate; 432 } 433 434 void clock_enable(enum periph_id clkid) 435 { 436 clock_set_enable(clkid, 1); 437 } 438 439 void clock_disable(enum periph_id clkid) 440 { 441 clock_set_enable(clkid, 0); 442 } 443 444 void reset_periph(enum periph_id periph_id, int us_delay) 445 { 446 /* Put peripheral into reset */ 447 reset_set_enable(periph_id, 1); 448 udelay(us_delay); 449 450 /* Remove reset */ 451 reset_set_enable(periph_id, 0); 452 453 udelay(us_delay); 454 } 455 456 void reset_cmplx_set_enable(int cpu, int which, int reset) 457 { 458 struct clk_rst_ctlr *clkrst = 459 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 460 u32 mask; 461 462 /* Form the mask, which depends on the cpu chosen (2 or 4) */ 463 assert(cpu >= 0 && cpu < MAX_NUM_CPU); 464 mask = which << cpu; 465 466 /* either enable or disable those reset for that CPU */ 467 if (reset) 468 writel(mask, &clkrst->crc_cpu_cmplx_set); 469 else 470 writel(mask, &clkrst->crc_cpu_cmplx_clr); 471 } 472 473 unsigned clock_get_rate(enum clock_id clkid) 474 { 475 struct clk_pll *pll; 476 u32 base; 477 u32 divm; 478 u64 parent_rate; 479 u64 rate; 480 481 parent_rate = osc_freq[clock_get_osc_freq()]; 482 if (clkid == CLOCK_ID_OSC) 483 return parent_rate; 484 485 pll = get_pll(clkid); 486 if (!pll) 487 return 0; 488 base = readl(&pll->pll_base); 489 490 /* Oh for bf_unpack()... */ 491 rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT); 492 divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT; 493 if (clkid == CLOCK_ID_USB) 494 divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT; 495 else 496 divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT; 497 do_div(rate, divm); 498 return rate; 499 } 500 501 /** 502 * Set the output frequency you want for each PLL clock. 503 * PLL output frequencies are programmed by setting their N, M and P values. 504 * The governing equations are: 505 * VCO = (Fi / m) * n, Fo = VCO / (2^p) 506 * where Fo is the output frequency from the PLL. 507 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) 508 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 509 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming 510 * 511 * @param n PLL feedback divider(DIVN) 512 * @param m PLL input divider(DIVN) 513 * @param p post divider(DIVP) 514 * @param cpcon base PLL charge pump(CPCON) 515 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot 516 * be overriden), 1 if PLL is already correct 517 */ 518 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) 519 { 520 u32 base_reg; 521 u32 misc_reg; 522 struct clk_pll *pll; 523 524 pll = get_pll(clkid); 525 526 base_reg = readl(&pll->pll_base); 527 528 /* Set BYPASS, m, n and p to PLL_BASE */ 529 base_reg &= ~PLL_DIVM_MASK; 530 base_reg |= m << PLL_DIVM_SHIFT; 531 532 base_reg &= ~PLL_DIVN_MASK; 533 base_reg |= n << PLL_DIVN_SHIFT; 534 535 base_reg &= ~PLL_DIVP_MASK; 536 base_reg |= p << PLL_DIVP_SHIFT; 537 538 if (clkid == CLOCK_ID_PERIPH) { 539 /* 540 * If the PLL is already set up, check that it is correct 541 * and record this info for clock_verify() to check. 542 */ 543 if (base_reg & PLL_BASE_OVRRIDE_MASK) { 544 base_reg |= PLL_ENABLE_MASK; 545 if (base_reg != readl(&pll->pll_base)) 546 pllp_valid = 0; 547 return pllp_valid ? 1 : -1; 548 } 549 base_reg |= PLL_BASE_OVRRIDE_MASK; 550 } 551 552 base_reg |= PLL_BYPASS_MASK; 553 writel(base_reg, &pll->pll_base); 554 555 /* Set cpcon to PLL_MISC */ 556 misc_reg = readl(&pll->pll_misc); 557 #if !defined(CONFIG_TEGRA210) 558 misc_reg &= ~PLL_CPCON_MASK; 559 misc_reg |= cpcon << PLL_CPCON_SHIFT; 560 #else 561 /* T210 uses KCP instead, use the most common bit shift (PLLA/U/D2) */ 562 misc_reg &= ~PLLU_KCP_MASK; 563 misc_reg |= cpcon << PLLU_KCP_SHIFT; 564 #endif 565 566 writel(misc_reg, &pll->pll_misc); 567 568 /* Enable PLL */ 569 base_reg |= PLL_ENABLE_MASK; 570 writel(base_reg, &pll->pll_base); 571 572 /* Disable BYPASS */ 573 base_reg &= ~PLL_BYPASS_MASK; 574 writel(base_reg, &pll->pll_base); 575 576 return 0; 577 } 578 579 void clock_ll_start_uart(enum periph_id periph_id) 580 { 581 /* Assert UART reset and enable clock */ 582 reset_set_enable(periph_id, 1); 583 clock_enable(periph_id); 584 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */ 585 586 /* wait for 2us */ 587 udelay(2); 588 589 /* De-assert reset to UART */ 590 reset_set_enable(periph_id, 0); 591 } 592 593 #ifdef CONFIG_OF_CONTROL 594 int clock_decode_periph_id(const void *blob, int node) 595 { 596 enum periph_id id; 597 u32 cell[2]; 598 int err; 599 600 err = fdtdec_get_int_array(blob, node, "clocks", cell, 601 ARRAY_SIZE(cell)); 602 if (err) 603 return -1; 604 id = clk_id_to_periph_id(cell[1]); 605 assert(clock_periph_id_isvalid(id)); 606 return id; 607 } 608 #endif /* CONFIG_OF_CONTROL */ 609 610 int clock_verify(void) 611 { 612 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); 613 u32 reg = readl(&pll->pll_base); 614 615 if (!pllp_valid) { 616 printf("Warning: PLLP %x is not correct\n", reg); 617 return -1; 618 } 619 debug("PLLP %x is correct\n", reg); 620 return 0; 621 } 622 623 void clock_init(void) 624 { 625 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); 626 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); 627 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); 628 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB); 629 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY); 630 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); 631 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; 632 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); 633 634 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); 635 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); 636 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); 637 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); 638 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]); 639 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]); 640 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); 641 } 642 643 static void set_avp_clock_source(u32 src) 644 { 645 struct clk_rst_ctlr *clkrst = 646 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 647 u32 val; 648 649 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | 650 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | 651 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | 652 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | 653 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); 654 writel(val, &clkrst->crc_sclk_brst_pol); 655 udelay(3); 656 } 657 658 /* 659 * This function is useful on Tegra30, and any later SoCs that have compatible 660 * PLLP configuration registers. 661 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c 662 */ 663 void tegra30_set_up_pllp(void) 664 { 665 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 666 u32 reg; 667 668 /* 669 * Based on the Tegra TRM, the system clock (which is the AVP clock) can 670 * run up to 275MHz. On power on, the default sytem clock source is set 671 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to 672 * 408MHz which is beyond system clock's upper limit. 673 * 674 * The fix is to set the system clock to CLK_M before initializing PLLP, 675 * and then switch back to PLLP_OUT4, which has an appropriate divider 676 * configured, after PLLP has been configured 677 */ 678 set_avp_clock_source(SCLK_SOURCE_CLKM); 679 680 /* 681 * PLLP output frequency set to 408Mhz 682 * PLLC output frequency set to 228Mhz 683 */ 684 switch (clock_get_osc_freq()) { 685 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ 686 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); 687 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); 688 break; 689 690 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ 691 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); 692 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); 693 break; 694 695 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ 696 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); 697 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); 698 break; 699 case CLOCK_OSC_FREQ_19_2: 700 default: 701 /* 702 * These are not supported. It is too early to print a 703 * message and the UART likely won't work anyway due to the 704 * oscillator being wrong. 705 */ 706 break; 707 } 708 709 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */ 710 711 /* OUT1, 2 */ 712 /* Assert RSTN before enable */ 713 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN; 714 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); 715 /* Set divisor and reenable */ 716 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) 717 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS 718 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) 719 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS; 720 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); 721 722 /* OUT3, 4 */ 723 /* Assert RSTN before enable */ 724 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; 725 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); 726 /* Set divisor and reenable */ 727 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) 728 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS 729 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) 730 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; 731 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); 732 733 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4); 734 } 735 736 int clock_external_output(int clk_id) 737 { 738 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 739 740 if (clk_id >= 1 && clk_id <= 3) { 741 setbits_le32(&pmc->pmc_clk_out_cntrl, 742 1 << (2 + (clk_id - 1) * 8)); 743 } else { 744 printf("%s: Unknown output clock id %d\n", __func__, clk_id); 745 return -EINVAL; 746 } 747 748 return 0; 749 } 750