109f455dcSMasahiro Yamada /* 209f455dcSMasahiro Yamada * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 309f455dcSMasahiro Yamada * 409f455dcSMasahiro Yamada * This program is free software; you can redistribute it and/or modify it 509f455dcSMasahiro Yamada * under the terms and conditions of the GNU General Public License, 609f455dcSMasahiro Yamada * version 2, as published by the Free Software Foundation. 709f455dcSMasahiro Yamada * 809f455dcSMasahiro Yamada * This program is distributed in the hope it will be useful, but WITHOUT 909f455dcSMasahiro Yamada * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1009f455dcSMasahiro Yamada * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1109f455dcSMasahiro Yamada * more details. 1209f455dcSMasahiro Yamada * 1309f455dcSMasahiro Yamada * You should have received a copy of the GNU General Public License 1409f455dcSMasahiro Yamada * along with this program. If not, see <http://www.gnu.org/licenses/>. 1509f455dcSMasahiro Yamada */ 1609f455dcSMasahiro Yamada 1709f455dcSMasahiro Yamada /* Tegra cache routines */ 1809f455dcSMasahiro Yamada 1909f455dcSMasahiro Yamada #include <common.h> 2009f455dcSMasahiro Yamada #include <asm/io.h> 2109f455dcSMasahiro Yamada #include <asm/arch-tegra/ap.h> 2209f455dcSMasahiro Yamada #include <asm/arch/gp_padctrl.h> 2309f455dcSMasahiro Yamada 24*7aaa5a60STom Warren #ifndef CONFIG_ARM64 2509f455dcSMasahiro Yamada void config_cache(void) 2609f455dcSMasahiro Yamada { 2709f455dcSMasahiro Yamada u32 reg = 0; 2809f455dcSMasahiro Yamada 2909f455dcSMasahiro Yamada /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ 3009f455dcSMasahiro Yamada asm volatile( 3109f455dcSMasahiro Yamada "mrc p15, 0, r0, c1, c0, 1\n" 3209f455dcSMasahiro Yamada "orr r0, r0, #0x41\n" 3309f455dcSMasahiro Yamada "mcr p15, 0, r0, c1, c0, 1\n"); 3409f455dcSMasahiro Yamada 3509f455dcSMasahiro Yamada /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */ 3609f455dcSMasahiro Yamada if (tegra_get_chip() < CHIPID_TEGRA114) 3709f455dcSMasahiro Yamada return; 3809f455dcSMasahiro Yamada 3909f455dcSMasahiro Yamada /* 4009f455dcSMasahiro Yamada * Systems with an architectural L2 cache must not use the PL310. 4109f455dcSMasahiro Yamada * Config L2CTLR here for a data RAM latency of 3 cycles. 4209f455dcSMasahiro Yamada */ 4309f455dcSMasahiro Yamada asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); 4409f455dcSMasahiro Yamada reg &= ~7; 4509f455dcSMasahiro Yamada reg |= 2; 4609f455dcSMasahiro Yamada asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); 4709f455dcSMasahiro Yamada } 48*7aaa5a60STom Warren #endif 49