1*09f455dcSMasahiro Yamada /* 2*09f455dcSMasahiro Yamada * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 3*09f455dcSMasahiro Yamada * 4*09f455dcSMasahiro Yamada * This program is free software; you can redistribute it and/or modify it 5*09f455dcSMasahiro Yamada * under the terms and conditions of the GNU General Public License, 6*09f455dcSMasahiro Yamada * version 2, as published by the Free Software Foundation. 7*09f455dcSMasahiro Yamada * 8*09f455dcSMasahiro Yamada * This program is distributed in the hope it will be useful, but WITHOUT 9*09f455dcSMasahiro Yamada * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10*09f455dcSMasahiro Yamada * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11*09f455dcSMasahiro Yamada * more details. 12*09f455dcSMasahiro Yamada * 13*09f455dcSMasahiro Yamada * You should have received a copy of the GNU General Public License 14*09f455dcSMasahiro Yamada * along with this program. If not, see <http://www.gnu.org/licenses/>. 15*09f455dcSMasahiro Yamada */ 16*09f455dcSMasahiro Yamada 17*09f455dcSMasahiro Yamada /* Tegra cache routines */ 18*09f455dcSMasahiro Yamada 19*09f455dcSMasahiro Yamada #include <common.h> 20*09f455dcSMasahiro Yamada #include <asm/io.h> 21*09f455dcSMasahiro Yamada #include <asm/arch-tegra/ap.h> 22*09f455dcSMasahiro Yamada #include <asm/arch/gp_padctrl.h> 23*09f455dcSMasahiro Yamada 24*09f455dcSMasahiro Yamada void config_cache(void) 25*09f455dcSMasahiro Yamada { 26*09f455dcSMasahiro Yamada u32 reg = 0; 27*09f455dcSMasahiro Yamada 28*09f455dcSMasahiro Yamada /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ 29*09f455dcSMasahiro Yamada asm volatile( 30*09f455dcSMasahiro Yamada "mrc p15, 0, r0, c1, c0, 1\n" 31*09f455dcSMasahiro Yamada "orr r0, r0, #0x41\n" 32*09f455dcSMasahiro Yamada "mcr p15, 0, r0, c1, c0, 1\n"); 33*09f455dcSMasahiro Yamada 34*09f455dcSMasahiro Yamada /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */ 35*09f455dcSMasahiro Yamada if (tegra_get_chip() < CHIPID_TEGRA114) 36*09f455dcSMasahiro Yamada return; 37*09f455dcSMasahiro Yamada 38*09f455dcSMasahiro Yamada /* 39*09f455dcSMasahiro Yamada * Systems with an architectural L2 cache must not use the PL310. 40*09f455dcSMasahiro Yamada * Config L2CTLR here for a data RAM latency of 3 cycles. 41*09f455dcSMasahiro Yamada */ 42*09f455dcSMasahiro Yamada asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); 43*09f455dcSMasahiro Yamada reg &= ~7; 44*09f455dcSMasahiro Yamada reg |= 2; 45*09f455dcSMasahiro Yamada asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); 46*09f455dcSMasahiro Yamada } 47