109f455dcSMasahiro Yamada /*
209f455dcSMasahiro Yamada * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
309f455dcSMasahiro Yamada *
4*5b8031ccSTom Rini * SPDX-License-Identifier: GPL-2.0
509f455dcSMasahiro Yamada */
609f455dcSMasahiro Yamada
709f455dcSMasahiro Yamada /* Tegra cache routines */
809f455dcSMasahiro Yamada
909f455dcSMasahiro Yamada #include <common.h>
1009f455dcSMasahiro Yamada #include <asm/io.h>
1109f455dcSMasahiro Yamada #include <asm/arch-tegra/ap.h>
1209f455dcSMasahiro Yamada #include <asm/arch/gp_padctrl.h>
1309f455dcSMasahiro Yamada
147aaa5a60STom Warren #ifndef CONFIG_ARM64
config_cache(void)1509f455dcSMasahiro Yamada void config_cache(void)
1609f455dcSMasahiro Yamada {
1709f455dcSMasahiro Yamada u32 reg = 0;
1809f455dcSMasahiro Yamada
1909f455dcSMasahiro Yamada /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
2009f455dcSMasahiro Yamada asm volatile(
2109f455dcSMasahiro Yamada "mrc p15, 0, r0, c1, c0, 1\n"
2209f455dcSMasahiro Yamada "orr r0, r0, #0x41\n"
2309f455dcSMasahiro Yamada "mcr p15, 0, r0, c1, c0, 1\n");
2409f455dcSMasahiro Yamada
2509f455dcSMasahiro Yamada /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
2609f455dcSMasahiro Yamada if (tegra_get_chip() < CHIPID_TEGRA114)
2709f455dcSMasahiro Yamada return;
2809f455dcSMasahiro Yamada
2909f455dcSMasahiro Yamada /*
3009f455dcSMasahiro Yamada * Systems with an architectural L2 cache must not use the PL310.
3109f455dcSMasahiro Yamada * Config L2CTLR here for a data RAM latency of 3 cycles.
3209f455dcSMasahiro Yamada */
3309f455dcSMasahiro Yamada asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
3409f455dcSMasahiro Yamada reg &= ~7;
3509f455dcSMasahiro Yamada reg |= 2;
3609f455dcSMasahiro Yamada asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
3709f455dcSMasahiro Yamada }
387aaa5a60STom Warren #endif
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