1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <linux/compiler.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #ifdef CONFIG_LCD 16 #include <asm/arch/display.h> 17 #endif 18 #include <asm/arch/funcmux.h> 19 #include <asm/arch/pinmux.h> 20 #include <asm/arch/pmu.h> 21 #ifdef CONFIG_PWM_TEGRA 22 #include <asm/arch/pwm.h> 23 #endif 24 #include <asm/arch/tegra.h> 25 #include <asm/arch-tegra/ap.h> 26 #include <asm/arch-tegra/board.h> 27 #include <asm/arch-tegra/clk_rst.h> 28 #include <asm/arch-tegra/pmc.h> 29 #include <asm/arch-tegra/sys_proto.h> 30 #include <asm/arch-tegra/uart.h> 31 #include <asm/arch-tegra/warmboot.h> 32 #ifdef CONFIG_TEGRA_CLOCK_SCALING 33 #include <asm/arch/emc.h> 34 #endif 35 #ifdef CONFIG_USB_EHCI_TEGRA 36 #include <asm/arch-tegra/usb.h> 37 #include <usb.h> 38 #endif 39 #ifdef CONFIG_TEGRA_MMC 40 #include <asm/arch-tegra/tegra_mmc.h> 41 #include <asm/arch-tegra/mmc.h> 42 #endif 43 #include <asm/arch-tegra/xusb-padctl.h> 44 #include <power/as3722.h> 45 #include <i2c.h> 46 #include <spi.h> 47 #include "emc.h" 48 49 DECLARE_GLOBAL_DATA_PTR; 50 51 #ifdef CONFIG_SPL_BUILD 52 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 53 U_BOOT_DEVICE(tegra_gpios) = { 54 "gpio_tegra" 55 }; 56 #endif 57 58 __weak void pinmux_init(void) {} 59 __weak void pin_mux_usb(void) {} 60 __weak void pin_mux_spi(void) {} 61 __weak void gpio_early_init_uart(void) {} 62 __weak void pin_mux_display(void) {} 63 __weak void start_cpu_fan(void) {} 64 65 #if defined(CONFIG_TEGRA_NAND) 66 __weak void pin_mux_nand(void) 67 { 68 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 69 } 70 #endif 71 72 /* 73 * Routine: power_det_init 74 * Description: turn off power detects 75 */ 76 static void power_det_init(void) 77 { 78 #if defined(CONFIG_TEGRA20) 79 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 80 81 /* turn off power detects */ 82 writel(0, &pmc->pmc_pwr_det_latch); 83 writel(0, &pmc->pmc_pwr_det); 84 #endif 85 } 86 87 __weak int tegra_board_id(void) 88 { 89 return -1; 90 } 91 92 #ifdef CONFIG_DISPLAY_BOARDINFO 93 int checkboard(void) 94 { 95 int board_id = tegra_board_id(); 96 97 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 98 if (board_id != -1) 99 printf(", ID: %d\n", board_id); 100 printf("\n"); 101 102 return 0; 103 } 104 #endif /* CONFIG_DISPLAY_BOARDINFO */ 105 106 __weak int tegra_lcd_pmic_init(int board_it) 107 { 108 return 0; 109 } 110 111 __weak int nvidia_board_init(void) 112 { 113 return 0; 114 } 115 116 /* 117 * Routine: board_init 118 * Description: Early hardware init. 119 */ 120 int board_init(void) 121 { 122 __maybe_unused int err; 123 __maybe_unused int board_id; 124 125 /* Do clocks and UART first so that printf() works */ 126 clock_init(); 127 clock_verify(); 128 129 #ifdef CONFIG_TEGRA_SPI 130 pin_mux_spi(); 131 #endif 132 133 #ifdef CONFIG_PWM_TEGRA 134 if (pwm_init(gd->fdt_blob)) 135 debug("%s: Failed to init pwm\n", __func__); 136 #endif 137 #ifdef CONFIG_LCD 138 pin_mux_display(); 139 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 140 #endif 141 /* boot param addr */ 142 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 143 144 power_det_init(); 145 146 #ifdef CONFIG_SYS_I2C_TEGRA 147 # ifdef CONFIG_TEGRA_PMU 148 if (pmu_set_nominal()) 149 debug("Failed to select nominal voltages\n"); 150 # ifdef CONFIG_TEGRA_CLOCK_SCALING 151 err = board_emc_init(); 152 if (err) 153 debug("Memory controller init failed: %d\n", err); 154 # endif 155 # endif /* CONFIG_TEGRA_PMU */ 156 #ifdef CONFIG_AS3722_POWER 157 err = as3722_init(NULL); 158 if (err && err != -ENODEV) 159 return err; 160 #endif 161 #endif /* CONFIG_SYS_I2C_TEGRA */ 162 163 #ifdef CONFIG_USB_EHCI_TEGRA 164 pin_mux_usb(); 165 #endif 166 167 #ifdef CONFIG_LCD 168 board_id = tegra_board_id(); 169 err = tegra_lcd_pmic_init(board_id); 170 if (err) 171 return err; 172 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 173 #endif 174 175 #ifdef CONFIG_TEGRA_NAND 176 pin_mux_nand(); 177 #endif 178 179 tegra_xusb_padctl_init(gd->fdt_blob); 180 181 #ifdef CONFIG_TEGRA_LP0 182 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 183 warmboot_save_sdram_params(); 184 185 /* prepare the WB code to LP0 location */ 186 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 187 #endif 188 return nvidia_board_init(); 189 } 190 191 #ifdef CONFIG_BOARD_EARLY_INIT_F 192 static void __gpio_early_init(void) 193 { 194 } 195 196 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 197 198 int board_early_init_f(void) 199 { 200 /* Do any special system timer/TSC setup */ 201 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 202 if (!tegra_cpu_is_non_secure()) 203 #endif 204 arch_timer_init(); 205 206 pinmux_init(); 207 board_init_uart_f(); 208 209 /* Initialize periph GPIOs */ 210 gpio_early_init(); 211 gpio_early_init_uart(); 212 #ifdef CONFIG_LCD 213 tegra_lcd_early_init(gd->fdt_blob); 214 #endif 215 216 return 0; 217 } 218 #endif /* EARLY_INIT */ 219 220 int board_late_init(void) 221 { 222 #ifdef CONFIG_LCD 223 /* Make sure we finish initing the LCD */ 224 tegra_lcd_check_next_stage(gd->fdt_blob, 1); 225 #endif 226 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 227 if (tegra_cpu_is_non_secure()) { 228 printf("CPU is in NS mode\n"); 229 setenv("cpu_ns_mode", "1"); 230 } else { 231 setenv("cpu_ns_mode", ""); 232 } 233 #endif 234 start_cpu_fan(); 235 236 return 0; 237 } 238 239 #if defined(CONFIG_TEGRA_MMC) 240 __weak void pin_mux_mmc(void) 241 { 242 } 243 244 /* this is a weak define that we are overriding */ 245 int board_mmc_init(bd_t *bd) 246 { 247 debug("%s called\n", __func__); 248 249 /* Enable muxes, etc. for SDMMC controllers */ 250 pin_mux_mmc(); 251 252 debug("%s: init MMC\n", __func__); 253 tegra_mmc_init(); 254 255 return 0; 256 } 257 258 void pad_init_mmc(struct mmc_host *host) 259 { 260 #if defined(CONFIG_TEGRA30) 261 enum periph_id id = host->mmc_id; 262 u32 val; 263 264 debug("%s: sdmmc address = %08x, id = %d\n", __func__, 265 (unsigned int)host->reg, id); 266 267 /* Set the pad drive strength for SDMMC1 or 3 only */ 268 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { 269 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 270 __func__); 271 return; 272 } 273 274 val = readl(&host->reg->sdmemcmppadctl); 275 val &= 0xFFFFFFF0; 276 val |= MEMCOMP_PADCTRL_VREF; 277 writel(val, &host->reg->sdmemcmppadctl); 278 279 val = readl(&host->reg->autocalcfg); 280 val &= 0xFFFF0000; 281 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 282 writel(val, &host->reg->autocalcfg); 283 #endif /* T30 */ 284 } 285 #endif /* MMC */ 286 287 #ifdef CONFIG_ARM64 288 /* 289 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower 290 * 32-bits of the physical address space. Cap the maximum usable RAM area 291 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit 292 * boundary that most devices can address. 293 */ 294 ulong board_get_usable_ram_top(ulong total_size) 295 { 296 if (gd->ram_top > 0x100000000) 297 return 0x100000000; 298 299 return gd->ram_top; 300 } 301 #endif 302