1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <linux/compiler.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #ifdef CONFIG_LCD 16 #include <asm/arch/display.h> 17 #endif 18 #include <asm/arch/funcmux.h> 19 #include <asm/arch/pinmux.h> 20 #include <asm/arch/pmu.h> 21 #ifdef CONFIG_PWM_TEGRA 22 #include <asm/arch/pwm.h> 23 #endif 24 #include <asm/arch/tegra.h> 25 #include <asm/arch-tegra/ap.h> 26 #include <asm/arch-tegra/board.h> 27 #include <asm/arch-tegra/clk_rst.h> 28 #include <asm/arch-tegra/pmc.h> 29 #include <asm/arch-tegra/sys_proto.h> 30 #include <asm/arch-tegra/uart.h> 31 #include <asm/arch-tegra/warmboot.h> 32 #ifdef CONFIG_TEGRA_CLOCK_SCALING 33 #include <asm/arch/emc.h> 34 #endif 35 #ifdef CONFIG_USB_EHCI_TEGRA 36 #include <asm/arch-tegra/usb.h> 37 #include <usb.h> 38 #endif 39 #ifdef CONFIG_TEGRA_MMC 40 #include <asm/arch-tegra/tegra_mmc.h> 41 #include <asm/arch-tegra/mmc.h> 42 #endif 43 #include <asm/arch-tegra/xusb-padctl.h> 44 #include <power/as3722.h> 45 #include <i2c.h> 46 #include <spi.h> 47 #include "emc.h" 48 49 DECLARE_GLOBAL_DATA_PTR; 50 51 #ifdef CONFIG_SPL_BUILD 52 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 53 U_BOOT_DEVICE(tegra_gpios) = { 54 "gpio_tegra" 55 }; 56 #endif 57 58 __weak void pinmux_init(void) {} 59 __weak void pin_mux_usb(void) {} 60 __weak void pin_mux_spi(void) {} 61 __weak void gpio_early_init_uart(void) {} 62 __weak void pin_mux_display(void) {} 63 64 #if defined(CONFIG_TEGRA_NAND) 65 __weak void pin_mux_nand(void) 66 { 67 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 68 } 69 #endif 70 71 /* 72 * Routine: power_det_init 73 * Description: turn off power detects 74 */ 75 static void power_det_init(void) 76 { 77 #if defined(CONFIG_TEGRA20) 78 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 79 80 /* turn off power detects */ 81 writel(0, &pmc->pmc_pwr_det_latch); 82 writel(0, &pmc->pmc_pwr_det); 83 #endif 84 } 85 86 __weak int tegra_board_id(void) 87 { 88 return -1; 89 } 90 91 #ifdef CONFIG_DISPLAY_BOARDINFO 92 int checkboard(void) 93 { 94 int board_id = tegra_board_id(); 95 96 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 97 if (board_id != -1) 98 printf(", ID: %d\n", board_id); 99 printf("\n"); 100 101 return 0; 102 } 103 #endif /* CONFIG_DISPLAY_BOARDINFO */ 104 105 __weak int tegra_lcd_pmic_init(int board_it) 106 { 107 return 0; 108 } 109 110 __weak int nvidia_board_init(void) 111 { 112 return 0; 113 } 114 115 /* 116 * Routine: board_init 117 * Description: Early hardware init. 118 */ 119 int board_init(void) 120 { 121 __maybe_unused int err; 122 __maybe_unused int board_id; 123 124 /* Do clocks and UART first so that printf() works */ 125 clock_init(); 126 clock_verify(); 127 128 #ifdef CONFIG_TEGRA_SPI 129 pin_mux_spi(); 130 #endif 131 132 #ifdef CONFIG_PWM_TEGRA 133 if (pwm_init(gd->fdt_blob)) 134 debug("%s: Failed to init pwm\n", __func__); 135 #endif 136 #ifdef CONFIG_LCD 137 pin_mux_display(); 138 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 139 #endif 140 /* boot param addr */ 141 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 142 143 power_det_init(); 144 145 #ifdef CONFIG_SYS_I2C_TEGRA 146 # ifdef CONFIG_TEGRA_PMU 147 if (pmu_set_nominal()) 148 debug("Failed to select nominal voltages\n"); 149 # ifdef CONFIG_TEGRA_CLOCK_SCALING 150 err = board_emc_init(); 151 if (err) 152 debug("Memory controller init failed: %d\n", err); 153 # endif 154 # endif /* CONFIG_TEGRA_PMU */ 155 #ifdef CONFIG_AS3722_POWER 156 err = as3722_init(NULL); 157 if (err && err != -ENODEV) 158 return err; 159 #endif 160 #endif /* CONFIG_SYS_I2C_TEGRA */ 161 162 #ifdef CONFIG_USB_EHCI_TEGRA 163 pin_mux_usb(); 164 # ifndef CONFIG_DM_USB 165 usb_process_devicetree(gd->fdt_blob); 166 # endif 167 #endif 168 169 #ifdef CONFIG_LCD 170 board_id = tegra_board_id(); 171 err = tegra_lcd_pmic_init(board_id); 172 if (err) 173 return err; 174 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 175 #endif 176 177 #ifdef CONFIG_TEGRA_NAND 178 pin_mux_nand(); 179 #endif 180 181 tegra_xusb_padctl_init(gd->fdt_blob); 182 183 #ifdef CONFIG_TEGRA_LP0 184 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 185 warmboot_save_sdram_params(); 186 187 /* prepare the WB code to LP0 location */ 188 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 189 #endif 190 return nvidia_board_init(); 191 } 192 193 #ifdef CONFIG_BOARD_EARLY_INIT_F 194 static void __gpio_early_init(void) 195 { 196 } 197 198 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 199 200 int board_early_init_f(void) 201 { 202 pinmux_init(); 203 board_init_uart_f(); 204 205 /* Initialize periph GPIOs */ 206 gpio_early_init(); 207 gpio_early_init_uart(); 208 #ifdef CONFIG_LCD 209 tegra_lcd_early_init(gd->fdt_blob); 210 #endif 211 212 return 0; 213 } 214 #endif /* EARLY_INIT */ 215 216 int board_late_init(void) 217 { 218 #ifdef CONFIG_LCD 219 /* Make sure we finish initing the LCD */ 220 tegra_lcd_check_next_stage(gd->fdt_blob, 1); 221 #endif 222 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 223 if (tegra_cpu_is_non_secure()) { 224 printf("CPU is in NS mode\n"); 225 setenv("cpu_ns_mode", "1"); 226 } else { 227 setenv("cpu_ns_mode", ""); 228 } 229 #endif 230 return 0; 231 } 232 233 #if defined(CONFIG_TEGRA_MMC) 234 __weak void pin_mux_mmc(void) 235 { 236 } 237 238 /* this is a weak define that we are overriding */ 239 int board_mmc_init(bd_t *bd) 240 { 241 debug("%s called\n", __func__); 242 243 /* Enable muxes, etc. for SDMMC controllers */ 244 pin_mux_mmc(); 245 246 debug("%s: init MMC\n", __func__); 247 tegra_mmc_init(); 248 249 return 0; 250 } 251 252 void pad_init_mmc(struct mmc_host *host) 253 { 254 #if defined(CONFIG_TEGRA30) 255 enum periph_id id = host->mmc_id; 256 u32 val; 257 258 debug("%s: sdmmc address = %08x, id = %d\n", __func__, 259 (unsigned int)host->reg, id); 260 261 /* Set the pad drive strength for SDMMC1 or 3 only */ 262 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { 263 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 264 __func__); 265 return; 266 } 267 268 val = readl(&host->reg->sdmemcmppadctl); 269 val &= 0xFFFFFFF0; 270 val |= MEMCOMP_PADCTRL_VREF; 271 writel(val, &host->reg->sdmemcmppadctl); 272 273 val = readl(&host->reg->autocalcfg); 274 val &= 0xFFFF0000; 275 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 276 writel(val, &host->reg->autocalcfg); 277 #endif /* T30 */ 278 } 279 #endif /* MMC */ 280