1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <usb.h> 13 #include <asm/io.h> 14 #include <asm/arch-tegra/ap.h> 15 #include <asm/arch-tegra/board.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <asm/arch-tegra/pmc.h> 18 #include <asm/arch-tegra/sys_proto.h> 19 #include <asm/arch-tegra/uart.h> 20 #include <asm/arch-tegra/warmboot.h> 21 #include <asm/arch-tegra/gpu.h> 22 #include <asm/arch-tegra/usb.h> 23 #include <asm/arch-tegra/xusb-padctl.h> 24 #include <asm/arch/clock.h> 25 #include <asm/arch/funcmux.h> 26 #include <asm/arch/pinmux.h> 27 #include <asm/arch/pmu.h> 28 #include <asm/arch/tegra.h> 29 #ifdef CONFIG_TEGRA_CLOCK_SCALING 30 #include <asm/arch/emc.h> 31 #endif 32 #include <power/as3722.h> 33 #include "emc.h" 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifdef CONFIG_SPL_BUILD 38 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 39 U_BOOT_DEVICE(tegra_gpios) = { 40 "gpio_tegra" 41 }; 42 #endif 43 44 __weak void pinmux_init(void) {} 45 __weak void pin_mux_usb(void) {} 46 __weak void pin_mux_spi(void) {} 47 __weak void pin_mux_mmc(void) {} 48 __weak void gpio_early_init_uart(void) {} 49 __weak void pin_mux_display(void) {} 50 __weak void start_cpu_fan(void) {} 51 52 #if defined(CONFIG_TEGRA_NAND) 53 __weak void pin_mux_nand(void) 54 { 55 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 56 } 57 #endif 58 59 /* 60 * Routine: power_det_init 61 * Description: turn off power detects 62 */ 63 static void power_det_init(void) 64 { 65 #if defined(CONFIG_TEGRA20) 66 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 67 68 /* turn off power detects */ 69 writel(0, &pmc->pmc_pwr_det_latch); 70 writel(0, &pmc->pmc_pwr_det); 71 #endif 72 } 73 74 __weak int tegra_board_id(void) 75 { 76 return -1; 77 } 78 79 #ifdef CONFIG_DISPLAY_BOARDINFO 80 int checkboard(void) 81 { 82 int board_id = tegra_board_id(); 83 84 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 85 if (board_id != -1) 86 printf(", ID: %d\n", board_id); 87 printf("\n"); 88 89 return 0; 90 } 91 #endif /* CONFIG_DISPLAY_BOARDINFO */ 92 93 __weak int tegra_lcd_pmic_init(int board_it) 94 { 95 return 0; 96 } 97 98 __weak int nvidia_board_init(void) 99 { 100 return 0; 101 } 102 103 /* 104 * Routine: board_init 105 * Description: Early hardware init. 106 */ 107 int board_init(void) 108 { 109 __maybe_unused int err; 110 __maybe_unused int board_id; 111 112 /* Do clocks and UART first so that printf() works */ 113 clock_init(); 114 clock_verify(); 115 116 tegra_gpu_config(); 117 118 #ifdef CONFIG_TEGRA_SPI 119 pin_mux_spi(); 120 #endif 121 122 #ifdef CONFIG_MMC_SDHCI_TEGRA 123 pin_mux_mmc(); 124 #endif 125 126 /* Init is handled automatically in the driver-model case */ 127 #if defined(CONFIG_DM_VIDEO) 128 pin_mux_display(); 129 #endif 130 /* boot param addr */ 131 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 132 133 power_det_init(); 134 135 #ifdef CONFIG_SYS_I2C_TEGRA 136 # ifdef CONFIG_TEGRA_PMU 137 if (pmu_set_nominal()) 138 debug("Failed to select nominal voltages\n"); 139 # ifdef CONFIG_TEGRA_CLOCK_SCALING 140 err = board_emc_init(); 141 if (err) 142 debug("Memory controller init failed: %d\n", err); 143 # endif 144 # endif /* CONFIG_TEGRA_PMU */ 145 #ifdef CONFIG_PMIC_AS3722 146 err = as3722_init(NULL); 147 if (err && err != -ENODEV) 148 return err; 149 #endif 150 #endif /* CONFIG_SYS_I2C_TEGRA */ 151 152 #ifdef CONFIG_USB_EHCI_TEGRA 153 pin_mux_usb(); 154 #endif 155 156 #if defined(CONFIG_DM_VIDEO) 157 board_id = tegra_board_id(); 158 err = tegra_lcd_pmic_init(board_id); 159 if (err) 160 return err; 161 #endif 162 163 #ifdef CONFIG_TEGRA_NAND 164 pin_mux_nand(); 165 #endif 166 167 tegra_xusb_padctl_init(gd->fdt_blob); 168 169 #ifdef CONFIG_TEGRA_LP0 170 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 171 warmboot_save_sdram_params(); 172 173 /* prepare the WB code to LP0 location */ 174 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 175 #endif 176 return nvidia_board_init(); 177 } 178 179 #ifdef CONFIG_BOARD_EARLY_INIT_F 180 static void __gpio_early_init(void) 181 { 182 } 183 184 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 185 186 int board_early_init_f(void) 187 { 188 if (!clock_early_init_done()) 189 clock_early_init(); 190 191 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) 192 #define USBCMD_FS2 (1 << 15) 193 { 194 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000; 195 writel(USBCMD_FS2, &usbctlr->usb_cmd); 196 } 197 #endif 198 199 /* Do any special system timer/TSC setup */ 200 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 201 if (!tegra_cpu_is_non_secure()) 202 #endif 203 arch_timer_init(); 204 205 pinmux_init(); 206 board_init_uart_f(); 207 208 /* Initialize periph GPIOs */ 209 gpio_early_init(); 210 gpio_early_init_uart(); 211 212 return 0; 213 } 214 #endif /* EARLY_INIT */ 215 216 int board_late_init(void) 217 { 218 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 219 if (tegra_cpu_is_non_secure()) { 220 printf("CPU is in NS mode\n"); 221 setenv("cpu_ns_mode", "1"); 222 } else { 223 setenv("cpu_ns_mode", ""); 224 } 225 #endif 226 start_cpu_fan(); 227 228 return 0; 229 } 230 231 /* 232 * In some SW environments, a memory carve-out exists to house a secure 233 * monitor, a trusted OS, and/or various statically allocated media buffers. 234 * 235 * This carveout exists at the highest possible address that is within a 236 * 32-bit physical address space. 237 * 238 * This function returns the total size of this carve-out. At present, the 239 * returned value is hard-coded for simplicity. In the future, it may be 240 * possible to determine the carve-out size: 241 * - By querying some run-time information source, such as: 242 * - A structure passed to U-Boot by earlier boot software. 243 * - SoC registers. 244 * - A call into the secure monitor. 245 * - In the per-board U-Boot configuration header, based on knowledge of the 246 * SW environment that U-Boot is being built for. 247 * 248 * For now, we support two configurations in U-Boot: 249 * - 32-bit ports without any form of carve-out. 250 * - 64 bit ports which are assumed to use a carve-out of a conservatively 251 * hard-coded size. 252 */ 253 static ulong carveout_size(void) 254 { 255 #ifdef CONFIG_ARM64 256 return SZ_512M; 257 #else 258 return 0; 259 #endif 260 } 261 262 /* 263 * Determine the amount of usable RAM below 4GiB, taking into account any 264 * carve-out that may be assigned. 265 */ 266 static ulong usable_ram_size_below_4g(void) 267 { 268 ulong total_size_below_4g; 269 ulong usable_size_below_4g; 270 271 /* 272 * The total size of RAM below 4GiB is the lesser address of: 273 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). 274 * (b) The size RAM physically present in the system. 275 */ 276 if (gd->ram_size < SZ_2G) 277 total_size_below_4g = gd->ram_size; 278 else 279 total_size_below_4g = SZ_2G; 280 281 /* Calculate usable RAM by subtracting out any carve-out size */ 282 usable_size_below_4g = total_size_below_4g - carveout_size(); 283 284 return usable_size_below_4g; 285 } 286 287 /* 288 * Represent all available RAM in either one or two banks. 289 * 290 * The first bank describes any usable RAM below 4GiB. 291 * The second bank describes any RAM above 4GiB. 292 * 293 * This split is driven by the following requirements: 294 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg 295 * property for memory below and above the 4GiB boundary. The layout of that 296 * DT property is directly driven by the entries in the U-Boot bank array. 297 * - The potential existence of a carve-out at the end of RAM below 4GiB can 298 * only be represented using multiple banks. 299 * 300 * Explicitly removing the carve-out RAM from the bank entries makes the RAM 301 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot 302 * command-line. 303 * 304 * This does mean that the DT U-Boot passes to the Linux kernel will not 305 * include this RAM in /memory/reg at all. An alternative would be to include 306 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node 307 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the 308 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU 309 * mapping, so either way is acceptable. 310 * 311 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the 312 * start address of that bank cannot be represented in the 32-bit .size 313 * field. 314 */ 315 int dram_init_banksize(void) 316 { 317 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 318 gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); 319 320 #ifdef CONFIG_PCI 321 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 322 #endif 323 324 #ifdef CONFIG_PHYS_64BIT 325 if (gd->ram_size > SZ_2G) { 326 gd->bd->bi_dram[1].start = 0x100000000; 327 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; 328 } else 329 #endif 330 { 331 gd->bd->bi_dram[1].start = 0; 332 gd->bd->bi_dram[1].size = 0; 333 } 334 335 return 0; 336 } 337 338 /* 339 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower 340 * 32-bits of the physical address space. Cap the maximum usable RAM area 341 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit 342 * boundary that most devices can address. Also, don't let U-Boot use any 343 * carve-out, as mentioned above. 344 * 345 * This function is called before dram_init_banksize(), so we can't simply 346 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. 347 */ 348 ulong board_get_usable_ram_top(ulong total_size) 349 { 350 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); 351 } 352