1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/funcmux.h> 12 #include <asm/arch/mc.h> 13 #include <asm/arch/tegra.h> 14 #include <asm/arch-tegra/board.h> 15 #include <asm/arch-tegra/pmc.h> 16 #include <asm/arch-tegra/sys_proto.h> 17 #include <asm/arch-tegra/warmboot.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 enum { 22 /* UARTs which we can enable */ 23 UARTA = 1 << 0, 24 UARTB = 1 << 1, 25 UARTC = 1 << 2, 26 UARTD = 1 << 3, 27 UARTE = 1 << 4, 28 UART_COUNT = 5, 29 }; 30 31 /* Read the RAM size directly from the memory controller */ 32 unsigned int query_sdram_size(void) 33 { 34 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE; 35 u32 emem_cfg, size_bytes; 36 37 emem_cfg = readl(&mc->mc_emem_cfg); 38 #if defined(CONFIG_TEGRA20) 39 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg); 40 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024); 41 #else 42 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg); 43 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024 * 1024); 44 #endif 45 46 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) 47 /* External memory limited to 2047 MB due to IROM/HI-VEC */ 48 if (size_bytes == SZ_2G) 49 size_bytes -= SZ_1M; 50 #endif 51 52 return size_bytes; 53 } 54 55 int dram_init(void) 56 { 57 /* We do not initialise DRAM here. We just query the size */ 58 gd->ram_size = query_sdram_size(); 59 return 0; 60 } 61 62 #ifdef CONFIG_DISPLAY_BOARDINFO 63 int checkboard(void) 64 { 65 printf("Board: %s\n", sysinfo.board_string); 66 return 0; 67 } 68 #endif /* CONFIG_DISPLAY_BOARDINFO */ 69 70 static int uart_configs[] = { 71 #if defined(CONFIG_TEGRA20) 72 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) 73 FUNCMUX_UART1_UAA_UAB, 74 #elif defined(CONFIG_TEGRA_UARTA_GPU) 75 FUNCMUX_UART1_GPU, 76 #elif defined(CONFIG_TEGRA_UARTA_SDIO1) 77 FUNCMUX_UART1_SDIO1, 78 #else 79 FUNCMUX_UART1_IRRX_IRTX, 80 #endif 81 FUNCMUX_UART2_UAD, 82 -1, 83 FUNCMUX_UART4_GMC, 84 -1, 85 #elif defined(CONFIG_TEGRA30) 86 FUNCMUX_UART1_ULPI, /* UARTA */ 87 -1, 88 -1, 89 -1, 90 -1, 91 #elif defined(CONFIG_TEGRA114) 92 -1, 93 -1, 94 -1, 95 FUNCMUX_UART4_GMI, /* UARTD */ 96 -1, 97 #else /* Tegra124 */ 98 FUNCMUX_UART1_KBC, /* UARTA */ 99 -1, 100 -1, 101 FUNCMUX_UART4_GPIO, /* UARTD */ 102 -1, 103 #endif 104 }; 105 106 /** 107 * Set up the specified uarts 108 * 109 * @param uarts_ids Mask containing UARTs to init (UARTx) 110 */ 111 static void setup_uarts(int uart_ids) 112 { 113 static enum periph_id id_for_uart[] = { 114 PERIPH_ID_UART1, 115 PERIPH_ID_UART2, 116 PERIPH_ID_UART3, 117 PERIPH_ID_UART4, 118 PERIPH_ID_UART5, 119 }; 120 size_t i; 121 122 for (i = 0; i < UART_COUNT; i++) { 123 if (uart_ids & (1 << i)) { 124 enum periph_id id = id_for_uart[i]; 125 126 funcmux_select(id, uart_configs[i]); 127 clock_ll_start_uart(id); 128 } 129 } 130 } 131 132 void board_init_uart_f(void) 133 { 134 int uart_ids = 0; /* bit mask of which UART ids to enable */ 135 136 #ifdef CONFIG_TEGRA_ENABLE_UARTA 137 uart_ids |= UARTA; 138 #endif 139 #ifdef CONFIG_TEGRA_ENABLE_UARTB 140 uart_ids |= UARTB; 141 #endif 142 #ifdef CONFIG_TEGRA_ENABLE_UARTC 143 uart_ids |= UARTC; 144 #endif 145 #ifdef CONFIG_TEGRA_ENABLE_UARTD 146 uart_ids |= UARTD; 147 #endif 148 #ifdef CONFIG_TEGRA_ENABLE_UARTE 149 uart_ids |= UARTE; 150 #endif 151 setup_uarts(uart_ids); 152 } 153 154 #ifndef CONFIG_SYS_DCACHE_OFF 155 void enable_caches(void) 156 { 157 /* Enable D-cache. I-cache is already enabled in start.S */ 158 dcache_enable(); 159 } 160 #endif 161