1376cb1a4SStephen Warren /* 2376cb1a4SStephen Warren * (C) Copyright 2014 - 2015 Xilinx, Inc. 3376cb1a4SStephen Warren * Michal Simek <michal.simek@xilinx.com> 4376cb1a4SStephen Warren * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c) 5376cb1a4SStephen Warren * 6376cb1a4SStephen Warren * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 7376cb1a4SStephen Warren * 8376cb1a4SStephen Warren * SPDX-License-Identifier: GPL-2.0+ 9376cb1a4SStephen Warren */ 10376cb1a4SStephen Warren 11376cb1a4SStephen Warren #include <common.h> 12376cb1a4SStephen Warren #include <asm/system.h> 13376cb1a4SStephen Warren #include <asm/armv8/mmu.h> 14376cb1a4SStephen Warren 15b30291a3SAlexander Graf static struct mm_region tegra_mem_map[] = { 16376cb1a4SStephen Warren { 17cd4b0c5fSYork Sun .virt = 0x0UL, 18cd4b0c5fSYork Sun .phys = 0x0UL, 19b30291a3SAlexander Graf .size = 0x80000000UL, 20b30291a3SAlexander Graf .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 21b30291a3SAlexander Graf PTE_BLOCK_NON_SHARE | 22b30291a3SAlexander Graf PTE_BLOCK_PXN | PTE_BLOCK_UXN 23b30291a3SAlexander Graf }, { 24cd4b0c5fSYork Sun .virt = 0x80000000UL, 25cd4b0c5fSYork Sun .phys = 0x80000000UL, 26*d40d69eeSStephen Warren .size = 0x80000000UL, 27b30291a3SAlexander Graf .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 28b30291a3SAlexander Graf PTE_BLOCK_INNER_SHARE 29b30291a3SAlexander Graf }, { 30b30291a3SAlexander Graf /* List terminator */ 31b30291a3SAlexander Graf 0, 32376cb1a4SStephen Warren } 33b30291a3SAlexander Graf }; 34376cb1a4SStephen Warren 35b30291a3SAlexander Graf struct mm_region *mem_map = tegra_mem_map; 36