1 /* 2 * Sunxi usb-phy code 3 * 4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 5 * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com> 6 * 7 * Based on code from 8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/usb_phy.h> 17 #include <asm/gpio.h> 18 #include <asm/io.h> 19 #include <errno.h> 20 21 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800 22 #ifdef CONFIG_MACH_SUN8I_A33 23 #define SUNXI_USB_CSR 0x410 24 #else 25 #define SUNXI_USB_CSR 0x404 26 #endif 27 #define SUNXI_USB_PASSBY_EN 1 28 29 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10) 30 #define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9) 31 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8) 32 #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0) 33 34 #define REG_PHY_UNK_H3 0x420 35 #define REG_PMU_UNK_H3 0x810 36 37 /* A83T specific control bits for PHY0 */ 38 #define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5) 39 #define SUNXI_PHY_CTL_SIDDQ BIT(3) 40 41 /* A83T HSIC specific bits */ 42 #define SUNXI_EHCI_HS_FORCE BIT(20) 43 #define SUNXI_EHCI_CONNECT_DET BIT(17) 44 #define SUNXI_EHCI_CONNECT_INT BIT(16) 45 #define SUNXI_EHCI_HSIC BIT(1) 46 47 static struct sunxi_usb_phy { 48 int usb_rst_mask; 49 int gpio_vbus; 50 int gpio_vbus_det; 51 int gpio_id_det; 52 int id; 53 int init_count; 54 int power_on_count; 55 ulong base; 56 } sunxi_usb_phy[] = { 57 { 58 .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK, 59 .id = 0, 60 .base = SUNXI_USB0_BASE, 61 }, 62 { 63 .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK, 64 .id = 1, 65 .base = SUNXI_USB1_BASE, 66 }, 67 #if CONFIG_SUNXI_USB_PHYS >= 3 68 { 69 #ifdef CONFIG_MACH_SUN8I_A83T 70 .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK | 71 CCM_USB_CTRL_12M_CLK, 72 #else 73 .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, 74 #endif 75 .id = 2, 76 .base = SUNXI_USB2_BASE, 77 }, 78 #endif 79 #if CONFIG_SUNXI_USB_PHYS >= 4 80 { 81 .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK, 82 .id = 3, 83 .base = SUNXI_USB3_BASE, 84 } 85 #endif 86 }; 87 88 static int get_vbus_gpio(int index) 89 { 90 switch (index) { 91 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN); 92 case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN); 93 case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN); 94 case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN); 95 } 96 return -EINVAL; 97 } 98 99 static int get_vbus_detect_gpio(int index) 100 { 101 switch (index) { 102 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET); 103 } 104 return -EINVAL; 105 } 106 107 static int get_id_detect_gpio(int index) 108 { 109 switch (index) { 110 case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET); 111 } 112 return -EINVAL; 113 } 114 115 __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, 116 int data, int len) 117 { 118 int j = 0, usbc_bit = 0; 119 void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR; 120 121 #ifdef CONFIG_MACH_SUN8I_A33 122 /* CSR needs to be explicitly initialized to 0 on A33 */ 123 writel(0, dest); 124 #endif 125 126 usbc_bit = 1 << (phy->id * 2); 127 for (j = 0; j < len; j++) { 128 /* set the bit address to be written */ 129 clrbits_le32(dest, 0xff << 8); 130 setbits_le32(dest, (addr + j) << 8); 131 132 clrbits_le32(dest, usbc_bit); 133 /* set data bit */ 134 if (data & 0x1) 135 setbits_le32(dest, 1 << 7); 136 else 137 clrbits_le32(dest, 1 << 7); 138 139 setbits_le32(dest, usbc_bit); 140 141 clrbits_le32(dest, usbc_bit); 142 143 data >>= 1; 144 } 145 } 146 147 #if defined CONFIG_MACH_SUN8I_H3 148 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) 149 { 150 if (phy->id == 0) 151 clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); 152 153 clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); 154 } 155 #elif defined CONFIG_MACH_SUN8I_A83T 156 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) 157 { 158 } 159 #else 160 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) 161 { 162 /* The following comments are machine 163 * translated from Chinese, you have been warned! 164 */ 165 166 /* Regulation 45 ohms */ 167 if (phy->id == 0) 168 usb_phy_write(phy, 0x0c, 0x01, 1); 169 170 /* adjust PHY's magnitude and rate */ 171 usb_phy_write(phy, 0x20, 0x14, 5); 172 173 /* threshold adjustment disconnect */ 174 #if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I 175 usb_phy_write(phy, 0x2a, 2, 2); 176 #else 177 usb_phy_write(phy, 0x2a, 3, 2); 178 #endif 179 180 return; 181 } 182 #endif 183 184 static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable) 185 { 186 unsigned long bits = 0; 187 void *addr; 188 189 addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE; 190 191 bits = SUNXI_EHCI_AHB_ICHR8_EN | 192 SUNXI_EHCI_AHB_INCR4_BURST_EN | 193 SUNXI_EHCI_AHB_INCRX_ALIGN_EN | 194 SUNXI_EHCI_ULPI_BYPASS_EN; 195 196 #ifdef CONFIG_MACH_SUN8I_A83T 197 if (phy->id == 2) 198 bits |= SUNXI_EHCI_HS_FORCE | 199 SUNXI_EHCI_CONNECT_INT | 200 SUNXI_EHCI_HSIC; 201 #endif 202 203 if (enable) 204 setbits_le32(addr, bits); 205 else 206 clrbits_le32(addr, bits); 207 208 return; 209 } 210 211 void sunxi_usb_phy_enable_squelch_detect(int index, int enable) 212 { 213 #ifndef CONFIG_MACH_SUN8I_A83T 214 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 215 216 usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2); 217 #endif 218 } 219 220 void sunxi_usb_phy_init(int index) 221 { 222 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 223 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 224 225 phy->init_count++; 226 if (phy->init_count != 1) 227 return; 228 229 setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); 230 231 sunxi_usb_phy_config(phy); 232 233 if (phy->id != 0) 234 sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN); 235 236 #ifdef CONFIG_MACH_SUN8I_A83T 237 if (phy->id == 0) { 238 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, 239 SUNXI_PHY_CTL_VBUSVLDEXT); 240 clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, 241 SUNXI_PHY_CTL_SIDDQ); 242 } 243 #endif 244 } 245 246 void sunxi_usb_phy_exit(int index) 247 { 248 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 249 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 250 251 phy->init_count--; 252 if (phy->init_count != 0) 253 return; 254 255 if (phy->id != 0) 256 sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN); 257 258 #ifdef CONFIG_MACH_SUN8I_A83T 259 if (phy->id == 0) { 260 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, 261 SUNXI_PHY_CTL_SIDDQ); 262 } 263 #endif 264 265 clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); 266 } 267 268 void sunxi_usb_phy_power_on(int index) 269 { 270 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 271 272 phy->power_on_count++; 273 if (phy->power_on_count != 1) 274 return; 275 276 if (phy->gpio_vbus >= 0) 277 gpio_set_value(phy->gpio_vbus, 1); 278 } 279 280 void sunxi_usb_phy_power_off(int index) 281 { 282 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 283 284 phy->power_on_count--; 285 if (phy->power_on_count != 0) 286 return; 287 288 if (phy->gpio_vbus >= 0) 289 gpio_set_value(phy->gpio_vbus, 0); 290 } 291 292 int sunxi_usb_phy_power_is_on(int index) 293 { 294 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 295 296 return phy->power_on_count > 0; 297 } 298 299 int sunxi_usb_phy_vbus_detect(int index) 300 { 301 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 302 int err, retries = 3; 303 304 if (phy->gpio_vbus_det < 0) 305 return phy->gpio_vbus_det; 306 307 err = gpio_get_value(phy->gpio_vbus_det); 308 /* 309 * Vbus may have been provided by the board and just been turned of 310 * some milliseconds ago on reset, what we're measuring then is a 311 * residual charge on Vbus, sleep a bit and try again. 312 */ 313 while (err > 0 && retries--) { 314 mdelay(100); 315 err = gpio_get_value(phy->gpio_vbus_det); 316 } 317 318 return err; 319 } 320 321 int sunxi_usb_phy_id_detect(int index) 322 { 323 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 324 325 if (phy->gpio_id_det < 0) 326 return phy->gpio_id_det; 327 328 return gpio_get_value(phy->gpio_id_det); 329 } 330 331 int sunxi_usb_phy_probe(void) 332 { 333 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 334 struct sunxi_usb_phy *phy; 335 int i, ret = 0; 336 337 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { 338 phy = &sunxi_usb_phy[i]; 339 340 phy->gpio_vbus = get_vbus_gpio(i); 341 if (phy->gpio_vbus >= 0) { 342 ret = gpio_request(phy->gpio_vbus, "usb_vbus"); 343 if (ret) 344 return ret; 345 ret = gpio_direction_output(phy->gpio_vbus, 0); 346 if (ret) 347 return ret; 348 } 349 350 phy->gpio_vbus_det = get_vbus_detect_gpio(i); 351 if (phy->gpio_vbus_det >= 0) { 352 ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det"); 353 if (ret) 354 return ret; 355 ret = gpio_direction_input(phy->gpio_vbus_det); 356 if (ret) 357 return ret; 358 } 359 360 phy->gpio_id_det = get_id_detect_gpio(i); 361 if (phy->gpio_id_det >= 0) { 362 ret = gpio_request(phy->gpio_id_det, "usb_id_det"); 363 if (ret) 364 return ret; 365 ret = gpio_direction_input(phy->gpio_id_det); 366 if (ret) 367 return ret; 368 sunxi_gpio_set_pull(phy->gpio_id_det, 369 SUNXI_GPIO_PULL_UP); 370 } 371 } 372 373 setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); 374 375 return 0; 376 } 377 378 int sunxi_usb_phy_remove(void) 379 { 380 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 381 struct sunxi_usb_phy *phy; 382 int i; 383 384 clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); 385 386 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { 387 phy = &sunxi_usb_phy[i]; 388 389 if (phy->gpio_vbus >= 0) 390 gpio_free(phy->gpio_vbus); 391 392 if (phy->gpio_vbus_det >= 0) 393 gpio_free(phy->gpio_vbus_det); 394 395 if (phy->gpio_id_det >= 0) 396 gpio_free(phy->gpio_id_det); 397 } 398 399 return 0; 400 } 401