1 /* 2 * Sunxi usb-phy code 3 * 4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 5 * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com> 6 * 7 * Based on code from 8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/usb_phy.h> 17 #include <asm/gpio.h> 18 #include <asm/io.h> 19 #include <errno.h> 20 21 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800 22 #ifdef CONFIG_MACH_SUN8I_A33 23 #define SUNXI_USB_CSR 0x410 24 #else 25 #define SUNXI_USB_CSR 0x404 26 #endif 27 #define SUNXI_USB_PASSBY_EN 1 28 29 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10) 30 #define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9) 31 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8) 32 #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0) 33 34 #define REG_PHY_UNK_H3 0x420 35 #define REG_PMU_UNK_H3 0x810 36 37 /* A83T specific control bits for PHY0 */ 38 #define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5) 39 #define SUNXI_PHY_CTL_SIDDQ BIT(3) 40 41 /* A83T HSIC specific bits */ 42 #define SUNXI_EHCI_HS_FORCE BIT(20) 43 #define SUNXI_EHCI_CONNECT_DET BIT(17) 44 #define SUNXI_EHCI_CONNECT_INT BIT(16) 45 #define SUNXI_EHCI_HSIC BIT(1) 46 47 static struct sunxi_usb_phy { 48 int usb_rst_mask; 49 int gpio_vbus; 50 int gpio_vbus_det; 51 int gpio_id_det; 52 int id; 53 int init_count; 54 int power_on_count; 55 ulong base; 56 } sunxi_usb_phy[] = { 57 { 58 .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK, 59 .id = 0, 60 .base = SUNXI_USB0_BASE, 61 }, 62 { 63 .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK, 64 .id = 1, 65 .base = SUNXI_USB1_BASE, 66 }, 67 #if CONFIG_SUNXI_USB_PHYS >= 3 68 { 69 #ifdef CONFIG_MACH_SUN8I_A83T 70 .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK | 71 CCM_USB_CTRL_12M_CLK, 72 #else 73 .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, 74 #endif 75 .id = 2, 76 .base = SUNXI_USB2_BASE, 77 }, 78 #endif 79 #if CONFIG_SUNXI_USB_PHYS >= 4 80 { 81 .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK, 82 .id = 3, 83 .base = SUNXI_USB3_BASE, 84 } 85 #endif 86 }; 87 88 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY; 89 90 static int get_vbus_gpio(int index) 91 { 92 switch (index) { 93 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN); 94 case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN); 95 case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN); 96 case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN); 97 } 98 return -EINVAL; 99 } 100 101 static int get_vbus_detect_gpio(int index) 102 { 103 switch (index) { 104 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET); 105 } 106 return -EINVAL; 107 } 108 109 static int get_id_detect_gpio(int index) 110 { 111 switch (index) { 112 case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET); 113 } 114 return -EINVAL; 115 } 116 117 __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, 118 int data, int len) 119 { 120 int j = 0, usbc_bit = 0; 121 void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR; 122 123 #ifdef CONFIG_MACH_SUN8I_A33 124 /* CSR needs to be explicitly initialized to 0 on A33 */ 125 writel(0, dest); 126 #endif 127 128 usbc_bit = 1 << (phy->id * 2); 129 for (j = 0; j < len; j++) { 130 /* set the bit address to be written */ 131 clrbits_le32(dest, 0xff << 8); 132 setbits_le32(dest, (addr + j) << 8); 133 134 clrbits_le32(dest, usbc_bit); 135 /* set data bit */ 136 if (data & 0x1) 137 setbits_le32(dest, 1 << 7); 138 else 139 clrbits_le32(dest, 1 << 7); 140 141 setbits_le32(dest, usbc_bit); 142 143 clrbits_le32(dest, usbc_bit); 144 145 data >>= 1; 146 } 147 } 148 149 #if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I) 150 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) 151 { 152 #if defined CONFIG_MACH_SUN8I_H3 153 if (phy->id == 0) 154 clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); 155 #endif 156 clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); 157 } 158 #elif defined CONFIG_MACH_SUN8I_A83T 159 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) 160 { 161 } 162 #else 163 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) 164 { 165 /* The following comments are machine 166 * translated from Chinese, you have been warned! 167 */ 168 169 /* Regulation 45 ohms */ 170 if (phy->id == 0) 171 usb_phy_write(phy, 0x0c, 0x01, 1); 172 173 /* adjust PHY's magnitude and rate */ 174 usb_phy_write(phy, 0x20, 0x14, 5); 175 176 /* threshold adjustment disconnect */ 177 #if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I 178 usb_phy_write(phy, 0x2a, 2, 2); 179 #else 180 usb_phy_write(phy, 0x2a, 3, 2); 181 #endif 182 183 return; 184 } 185 #endif 186 187 static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable) 188 { 189 unsigned long bits = 0; 190 void *addr; 191 192 addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE; 193 194 bits = SUNXI_EHCI_AHB_ICHR8_EN | 195 SUNXI_EHCI_AHB_INCR4_BURST_EN | 196 SUNXI_EHCI_AHB_INCRX_ALIGN_EN | 197 SUNXI_EHCI_ULPI_BYPASS_EN; 198 199 #ifdef CONFIG_MACH_SUN8I_A83T 200 if (phy->id == 2) 201 bits |= SUNXI_EHCI_HS_FORCE | 202 SUNXI_EHCI_CONNECT_INT | 203 SUNXI_EHCI_HSIC; 204 #endif 205 206 if (enable) 207 setbits_le32(addr, bits); 208 else 209 clrbits_le32(addr, bits); 210 211 return; 212 } 213 214 void sunxi_usb_phy_enable_squelch_detect(int index, int enable) 215 { 216 #ifndef CONFIG_MACH_SUN8I_A83T 217 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 218 219 usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2); 220 #endif 221 } 222 223 void sunxi_usb_phy_init(int index) 224 { 225 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 226 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 227 228 phy->init_count++; 229 if (phy->init_count != 1) 230 return; 231 232 setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); 233 234 sunxi_usb_phy_config(phy); 235 236 if (phy->id != 0) 237 sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN); 238 239 #ifdef CONFIG_MACH_SUN8I_A83T 240 if (phy->id == 0) { 241 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, 242 SUNXI_PHY_CTL_VBUSVLDEXT); 243 clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, 244 SUNXI_PHY_CTL_SIDDQ); 245 } 246 #endif 247 } 248 249 void sunxi_usb_phy_exit(int index) 250 { 251 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 252 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 253 254 phy->init_count--; 255 if (phy->init_count != 0) 256 return; 257 258 if (phy->id != 0) 259 sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN); 260 261 #ifdef CONFIG_MACH_SUN8I_A83T 262 if (phy->id == 0) { 263 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, 264 SUNXI_PHY_CTL_SIDDQ); 265 } 266 #endif 267 268 clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); 269 } 270 271 void sunxi_usb_phy_power_on(int index) 272 { 273 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 274 275 if (initial_usb_scan_delay) { 276 mdelay(initial_usb_scan_delay); 277 initial_usb_scan_delay = 0; 278 } 279 280 phy->power_on_count++; 281 if (phy->power_on_count != 1) 282 return; 283 284 if (phy->gpio_vbus >= 0) 285 gpio_set_value(phy->gpio_vbus, 1); 286 } 287 288 void sunxi_usb_phy_power_off(int index) 289 { 290 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 291 292 phy->power_on_count--; 293 if (phy->power_on_count != 0) 294 return; 295 296 if (phy->gpio_vbus >= 0) 297 gpio_set_value(phy->gpio_vbus, 0); 298 } 299 300 int sunxi_usb_phy_vbus_detect(int index) 301 { 302 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 303 int err, retries = 3; 304 305 if (phy->gpio_vbus_det < 0) 306 return phy->gpio_vbus_det; 307 308 err = gpio_get_value(phy->gpio_vbus_det); 309 /* 310 * Vbus may have been provided by the board and just been turned of 311 * some milliseconds ago on reset, what we're measuring then is a 312 * residual charge on Vbus, sleep a bit and try again. 313 */ 314 while (err > 0 && retries--) { 315 mdelay(100); 316 err = gpio_get_value(phy->gpio_vbus_det); 317 } 318 319 return err; 320 } 321 322 int sunxi_usb_phy_id_detect(int index) 323 { 324 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; 325 326 if (phy->gpio_id_det < 0) 327 return phy->gpio_id_det; 328 329 return gpio_get_value(phy->gpio_id_det); 330 } 331 332 int sunxi_usb_phy_probe(void) 333 { 334 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 335 struct sunxi_usb_phy *phy; 336 int i, ret = 0; 337 338 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { 339 phy = &sunxi_usb_phy[i]; 340 341 phy->gpio_vbus = get_vbus_gpio(i); 342 if (phy->gpio_vbus >= 0) { 343 ret = gpio_request(phy->gpio_vbus, "usb_vbus"); 344 if (ret) 345 return ret; 346 ret = gpio_direction_output(phy->gpio_vbus, 0); 347 if (ret) 348 return ret; 349 } 350 351 phy->gpio_vbus_det = get_vbus_detect_gpio(i); 352 if (phy->gpio_vbus_det >= 0) { 353 ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det"); 354 if (ret) 355 return ret; 356 ret = gpio_direction_input(phy->gpio_vbus_det); 357 if (ret) 358 return ret; 359 } 360 361 phy->gpio_id_det = get_id_detect_gpio(i); 362 if (phy->gpio_id_det >= 0) { 363 ret = gpio_request(phy->gpio_id_det, "usb_id_det"); 364 if (ret) 365 return ret; 366 ret = gpio_direction_input(phy->gpio_id_det); 367 if (ret) 368 return ret; 369 sunxi_gpio_set_pull(phy->gpio_id_det, 370 SUNXI_GPIO_PULL_UP); 371 } 372 } 373 374 setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); 375 376 return 0; 377 } 378 379 int sunxi_usb_phy_remove(void) 380 { 381 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 382 struct sunxi_usb_phy *phy; 383 int i; 384 385 clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); 386 387 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { 388 phy = &sunxi_usb_phy[i]; 389 390 if (phy->gpio_vbus >= 0) 391 gpio_free(phy->gpio_vbus); 392 393 if (phy->gpio_vbus_det >= 0) 394 gpio_free(phy->gpio_vbus_det); 395 396 if (phy->gpio_id_det >= 0) 397 gpio_free(phy->gpio_id_det); 398 } 399 400 return 0; 401 } 402