1*e6e505b9SAlexander Graf /*
2*e6e505b9SAlexander Graf * Sunxi A31 Power Management Unit
3*e6e505b9SAlexander Graf *
4*e6e505b9SAlexander Graf * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
5*e6e505b9SAlexander Graf * http://linux-sunxi.org
6*e6e505b9SAlexander Graf *
7*e6e505b9SAlexander Graf * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
8*e6e505b9SAlexander Graf *
9*e6e505b9SAlexander Graf * (C) Copyright 2006-2013
10*e6e505b9SAlexander Graf * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
11*e6e505b9SAlexander Graf * Berg Xing <bergxing@allwinnertech.com>
12*e6e505b9SAlexander Graf * Tom Cubie <tangliang@allwinnertech.com>
13*e6e505b9SAlexander Graf *
14*e6e505b9SAlexander Graf * SPDX-License-Identifier: GPL-2.0+
15*e6e505b9SAlexander Graf */
16*e6e505b9SAlexander Graf
17*e6e505b9SAlexander Graf #include <common.h>
18*e6e505b9SAlexander Graf #include <errno.h>
19*e6e505b9SAlexander Graf #include <asm/io.h>
20*e6e505b9SAlexander Graf #include <asm/arch/cpu.h>
21*e6e505b9SAlexander Graf #include <asm/arch/gpio.h>
22*e6e505b9SAlexander Graf #include <asm/arch/p2wi.h>
23*e6e505b9SAlexander Graf #include <asm/arch/prcm.h>
24*e6e505b9SAlexander Graf #include <asm/arch/clock.h>
25*e6e505b9SAlexander Graf #include <asm/arch/sys_proto.h>
26*e6e505b9SAlexander Graf
p2wi_init(void)27*e6e505b9SAlexander Graf void p2wi_init(void)
28*e6e505b9SAlexander Graf {
29*e6e505b9SAlexander Graf struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
30*e6e505b9SAlexander Graf
31*e6e505b9SAlexander Graf /* Enable p2wi and PIO clk, and de-assert their resets */
32*e6e505b9SAlexander Graf prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
33*e6e505b9SAlexander Graf
34*e6e505b9SAlexander Graf sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
35*e6e505b9SAlexander Graf sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
36*e6e505b9SAlexander Graf
37*e6e505b9SAlexander Graf /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
38*e6e505b9SAlexander Graf writel(P2WI_CTRL_RESET, &p2wi->ctrl);
39*e6e505b9SAlexander Graf sdelay(0x100);
40*e6e505b9SAlexander Graf writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
41*e6e505b9SAlexander Graf &p2wi->cc);
42*e6e505b9SAlexander Graf }
43*e6e505b9SAlexander Graf
p2wi_change_to_p2wi_mode(u8 slave_addr,u8 ctrl_reg,u8 init_data)44*e6e505b9SAlexander Graf int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
45*e6e505b9SAlexander Graf {
46*e6e505b9SAlexander Graf struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
47*e6e505b9SAlexander Graf unsigned long tmo = timer_get_us() + 1000000;
48*e6e505b9SAlexander Graf
49*e6e505b9SAlexander Graf writel(P2WI_PM_DEV_ADDR(slave_addr) |
50*e6e505b9SAlexander Graf P2WI_PM_CTRL_ADDR(ctrl_reg) |
51*e6e505b9SAlexander Graf P2WI_PM_INIT_DATA(init_data) |
52*e6e505b9SAlexander Graf P2WI_PM_INIT_SEND,
53*e6e505b9SAlexander Graf &p2wi->pm);
54*e6e505b9SAlexander Graf
55*e6e505b9SAlexander Graf while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
56*e6e505b9SAlexander Graf if (timer_get_us() > tmo)
57*e6e505b9SAlexander Graf return -ETIME;
58*e6e505b9SAlexander Graf }
59*e6e505b9SAlexander Graf
60*e6e505b9SAlexander Graf return 0;
61*e6e505b9SAlexander Graf }
62*e6e505b9SAlexander Graf
p2wi_await_trans(void)63*e6e505b9SAlexander Graf static int p2wi_await_trans(void)
64*e6e505b9SAlexander Graf {
65*e6e505b9SAlexander Graf struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
66*e6e505b9SAlexander Graf unsigned long tmo = timer_get_us() + 1000000;
67*e6e505b9SAlexander Graf int ret;
68*e6e505b9SAlexander Graf u8 reg;
69*e6e505b9SAlexander Graf
70*e6e505b9SAlexander Graf while (1) {
71*e6e505b9SAlexander Graf reg = readl(&p2wi->status);
72*e6e505b9SAlexander Graf if (reg & P2WI_STAT_TRANS_ERR) {
73*e6e505b9SAlexander Graf ret = -EIO;
74*e6e505b9SAlexander Graf break;
75*e6e505b9SAlexander Graf }
76*e6e505b9SAlexander Graf if (reg & P2WI_STAT_TRANS_DONE) {
77*e6e505b9SAlexander Graf ret = 0;
78*e6e505b9SAlexander Graf break;
79*e6e505b9SAlexander Graf }
80*e6e505b9SAlexander Graf if (timer_get_us() > tmo) {
81*e6e505b9SAlexander Graf ret = -ETIME;
82*e6e505b9SAlexander Graf break;
83*e6e505b9SAlexander Graf }
84*e6e505b9SAlexander Graf }
85*e6e505b9SAlexander Graf writel(reg, &p2wi->status); /* Clear status bits */
86*e6e505b9SAlexander Graf return ret;
87*e6e505b9SAlexander Graf }
88*e6e505b9SAlexander Graf
p2wi_read(const u8 addr,u8 * data)89*e6e505b9SAlexander Graf int p2wi_read(const u8 addr, u8 *data)
90*e6e505b9SAlexander Graf {
91*e6e505b9SAlexander Graf struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
92*e6e505b9SAlexander Graf int ret;
93*e6e505b9SAlexander Graf
94*e6e505b9SAlexander Graf writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
95*e6e505b9SAlexander Graf writel(P2WI_DATA_NUM_BYTES(1) |
96*e6e505b9SAlexander Graf P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
97*e6e505b9SAlexander Graf writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
98*e6e505b9SAlexander Graf writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
99*e6e505b9SAlexander Graf
100*e6e505b9SAlexander Graf ret = p2wi_await_trans();
101*e6e505b9SAlexander Graf
102*e6e505b9SAlexander Graf *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
103*e6e505b9SAlexander Graf return ret;
104*e6e505b9SAlexander Graf }
105*e6e505b9SAlexander Graf
p2wi_write(const u8 addr,u8 data)106*e6e505b9SAlexander Graf int p2wi_write(const u8 addr, u8 data)
107*e6e505b9SAlexander Graf {
108*e6e505b9SAlexander Graf struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
109*e6e505b9SAlexander Graf
110*e6e505b9SAlexander Graf writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
111*e6e505b9SAlexander Graf writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
112*e6e505b9SAlexander Graf writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
113*e6e505b9SAlexander Graf writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
114*e6e505b9SAlexander Graf writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
115*e6e505b9SAlexander Graf
116*e6e505b9SAlexander Graf return p2wi_await_trans();
117*e6e505b9SAlexander Graf }
118