1 /* 2 * sun6i specific clock code 3 * 4 * (C) Copyright 2007-2012 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * Tom Cubie <tangliang@allwinnertech.com> 7 * 8 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/prcm.h> 17 #include <asm/arch/sys_proto.h> 18 19 #ifdef CONFIG_SPL_BUILD 20 void clock_init_safe(void) 21 { 22 struct sunxi_ccm_reg * const ccm = 23 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 24 25 #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) 26 struct sunxi_prcm_reg * const prcm = 27 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; 28 29 /* Set PLL ldo voltage without this PLL6 does not work properly */ 30 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, 31 PRCM_PLL_CTRL_LDO_KEY); 32 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, 33 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | 34 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); 35 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); 36 #endif 37 38 #ifdef CONFIG_MACH_SUN8I_R40 39 /* Set PLL lock enable bits and switch to old lock mode */ 40 writel(GENMASK(12, 0), &ccm->pll_lock_ctrl); 41 #endif 42 43 clock_set_pll1(408000000); 44 45 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); 46 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) 47 ; 48 49 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); 50 51 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); 52 if (IS_ENABLED(CONFIG_MACH_SUN6I)) 53 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); 54 } 55 #endif 56 57 void clock_init_sec(void) 58 { 59 #ifdef CONFIG_MACH_SUNXI_H3_H5 60 struct sunxi_ccm_reg * const ccm = 61 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 62 63 setbits_le32(&ccm->ccu_sec_switch, 64 CCM_SEC_SWITCH_MBUS_NONSEC | 65 CCM_SEC_SWITCH_BUS_NONSEC | 66 CCM_SEC_SWITCH_PLL_NONSEC); 67 #endif 68 } 69 70 void clock_init_uart(void) 71 { 72 #if CONFIG_CONS_INDEX < 5 73 struct sunxi_ccm_reg *const ccm = 74 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 75 76 /* uart clock source is apb2 */ 77 writel(APB2_CLK_SRC_OSC24M| 78 APB2_CLK_RATE_N_1| 79 APB2_CLK_RATE_M(1), 80 &ccm->apb2_div); 81 82 /* open the clock for uart */ 83 setbits_le32(&ccm->apb2_gate, 84 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + 85 CONFIG_CONS_INDEX - 1)); 86 87 /* deassert uart reset */ 88 setbits_le32(&ccm->apb2_reset_cfg, 89 1 << (APB2_RESET_UART_SHIFT + 90 CONFIG_CONS_INDEX - 1)); 91 #else 92 /* enable R_PIO and R_UART clocks, and de-assert resets */ 93 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); 94 #endif 95 } 96 97 #ifdef CONFIG_SPL_BUILD 98 void clock_set_pll1(unsigned int clk) 99 { 100 struct sunxi_ccm_reg * const ccm = 101 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 102 const int p = 0; 103 int k = 1; 104 int m = 1; 105 106 if (clk > 1152000000) { 107 k = 2; 108 } else if (clk > 768000000) { 109 k = 3; 110 m = 2; 111 } 112 113 /* Switch to 24MHz clock while changing PLL1 */ 114 writel(AXI_DIV_3 << AXI_DIV_SHIFT | 115 ATB_DIV_2 << ATB_DIV_SHIFT | 116 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, 117 &ccm->cpu_axi_cfg); 118 119 /* 120 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored) 121 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m 122 */ 123 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | 124 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | 125 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); 126 sdelay(200); 127 128 /* Switch CPU to PLL1 */ 129 writel(AXI_DIV_3 << AXI_DIV_SHIFT | 130 ATB_DIV_2 << ATB_DIV_SHIFT | 131 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, 132 &ccm->cpu_axi_cfg); 133 } 134 #endif 135 136 void clock_set_pll3(unsigned int clk) 137 { 138 struct sunxi_ccm_reg * const ccm = 139 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 140 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ 141 142 if (clk == 0) { 143 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); 144 return; 145 } 146 147 /* PLL3 rate = 24000000 * n / m */ 148 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | 149 CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m), 150 &ccm->pll3_cfg); 151 } 152 153 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) 154 { 155 struct sunxi_ccm_reg * const ccm = 156 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 157 const int max_n = 32; 158 int k = 1, m = 2; 159 160 #ifdef CONFIG_MACH_SUNXI_H3_H5 161 clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK | 162 CCM_PLL5_TUN_INIT_FREQ_MASK, 163 CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16)); 164 #endif 165 166 if (sigma_delta_enable) 167 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); 168 169 /* PLL5 rate = 24000000 * n * k / m */ 170 if (clk > 24000000 * k * max_n / m) { 171 m = 1; 172 if (clk > 24000000 * k * max_n / m) 173 k = 2; 174 } 175 writel(CCM_PLL5_CTRL_EN | 176 (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) | 177 CCM_PLL5_CTRL_UPD | 178 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | 179 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); 180 181 udelay(5500); 182 } 183 184 #ifdef CONFIG_MACH_SUN6I 185 void clock_set_mipi_pll(unsigned int clk) 186 { 187 struct sunxi_ccm_reg * const ccm = 188 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 189 unsigned int k, m, n, value, diff; 190 unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff; 191 unsigned int src = clock_get_pll3(); 192 193 /* All calculations are in KHz to avoid overflows */ 194 clk /= 1000; 195 src /= 1000; 196 197 /* Pick the closest lower clock */ 198 for (k = 1; k <= 4; k++) { 199 for (m = 1; m <= 16; m++) { 200 for (n = 1; n <= 16; n++) { 201 value = src * n * k / m; 202 if (value > clk) 203 continue; 204 205 diff = clk - value; 206 if (diff < best_diff) { 207 best_diff = diff; 208 best_k = k; 209 best_m = m; 210 best_n = n; 211 } 212 if (diff == 0) 213 goto done; 214 } 215 } 216 } 217 218 done: 219 writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN | 220 CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) | 221 CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg); 222 } 223 #endif 224 225 #if defined(CONFIG_MACH_SUN8I_A33) || \ 226 defined(CONFIG_MACH_SUN8I_R40) || \ 227 defined(CONFIG_MACH_SUN50I) 228 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) 229 { 230 struct sunxi_ccm_reg * const ccm = 231 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 232 233 if (sigma_delta_enable) 234 writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0); 235 236 writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD | 237 (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) | 238 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg); 239 240 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD) 241 ; 242 } 243 #endif 244 245 unsigned int clock_get_pll3(void) 246 { 247 struct sunxi_ccm_reg *const ccm = 248 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 249 uint32_t rval = readl(&ccm->pll3_cfg); 250 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1; 251 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1; 252 253 /* Multiply by 1000 after dividing by m to avoid integer overflows */ 254 return (24000 * n / m) * 1000; 255 } 256 257 unsigned int clock_get_pll6(void) 258 { 259 struct sunxi_ccm_reg *const ccm = 260 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 261 uint32_t rval = readl(&ccm->pll6_cfg); 262 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; 263 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; 264 return 24000000 * n * k / 2; 265 } 266 267 unsigned int clock_get_mipi_pll(void) 268 { 269 struct sunxi_ccm_reg *const ccm = 270 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 271 uint32_t rval = readl(&ccm->mipi_pll_cfg); 272 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1; 273 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1; 274 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1; 275 unsigned int src = clock_get_pll3(); 276 277 /* Multiply by 1000 after dividing by m to avoid integer overflows */ 278 return ((src / 1000) * n * k / m) * 1000; 279 } 280 281 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) 282 { 283 int pll = clock_get_pll6() * 2; 284 int div = 1; 285 286 while ((pll / div) > hz) 287 div++; 288 289 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div), 290 clk_cfg); 291 } 292