1 /* 2 * (C) Copyright 2015 3 * Kamil Lulko, <kamil.lulko@gmail.com> 4 * 5 * (C) Copyright 2014 6 * STMicroelectronics 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/io.h> 13 #include <asm/arch/stm32.h> 14 #include <asm/arch/stm32_periph.h> 15 16 #define RCC_CR_HSION (1 << 0) 17 #define RCC_CR_HSEON (1 << 16) 18 #define RCC_CR_HSERDY (1 << 17) 19 #define RCC_CR_HSEBYP (1 << 18) 20 #define RCC_CR_CSSON (1 << 19) 21 #define RCC_CR_PLLON (1 << 24) 22 #define RCC_CR_PLLRDY (1 << 25) 23 24 #define RCC_PLLCFGR_PLLM_MASK 0x3F 25 #define RCC_PLLCFGR_PLLN_MASK 0x7FC0 26 #define RCC_PLLCFGR_PLLP_MASK 0x30000 27 #define RCC_PLLCFGR_PLLQ_MASK 0xF000000 28 #define RCC_PLLCFGR_PLLSRC (1 << 22) 29 #define RCC_PLLCFGR_PLLN_SHIFT 6 30 #define RCC_PLLCFGR_PLLP_SHIFT 16 31 #define RCC_PLLCFGR_PLLQ_SHIFT 24 32 33 #define RCC_CFGR_AHB_PSC_MASK 0xF0 34 #define RCC_CFGR_APB1_PSC_MASK 0x1C00 35 #define RCC_CFGR_APB2_PSC_MASK 0xE000 36 #define RCC_CFGR_SW0 (1 << 0) 37 #define RCC_CFGR_SW1 (1 << 1) 38 #define RCC_CFGR_SW_MASK 0x3 39 #define RCC_CFGR_SW_HSI 0 40 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0 41 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1 42 #define RCC_CFGR_SWS0 (1 << 2) 43 #define RCC_CFGR_SWS1 (1 << 3) 44 #define RCC_CFGR_SWS_MASK 0xC 45 #define RCC_CFGR_SWS_HSI 0 46 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 47 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 48 #define RCC_CFGR_HPRE_SHIFT 4 49 #define RCC_CFGR_PPRE1_SHIFT 10 50 #define RCC_CFGR_PPRE2_SHIFT 13 51 52 #define RCC_APB1ENR_PWREN (1 << 28) 53 54 /* 55 * RCC USART specific definitions 56 */ 57 #define RCC_ENR_USART1EN (1 << 4) 58 #define RCC_ENR_USART2EN (1 << 17) 59 #define RCC_ENR_USART3EN (1 << 18) 60 #define RCC_ENR_USART6EN (1 << 5) 61 62 #define PWR_CR_VOS0 (1 << 14) 63 #define PWR_CR_VOS1 (1 << 15) 64 #define PWR_CR_VOS_MASK 0xC000 65 #define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1) 66 #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1) 67 #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0) 68 69 #define FLASH_ACR_WS(n) n 70 #define FLASH_ACR_PRFTEN (1 << 8) 71 #define FLASH_ACR_ICEN (1 << 9) 72 #define FLASH_ACR_DCEN (1 << 10) 73 74 /* 75 * RCC GPIO specific definitions 76 */ 77 #define RCC_ENR_GPIO_A_EN (1 << 0) 78 #define RCC_ENR_GPIO_B_EN (1 << 1) 79 #define RCC_ENR_GPIO_C_EN (1 << 2) 80 #define RCC_ENR_GPIO_D_EN (1 << 3) 81 #define RCC_ENR_GPIO_E_EN (1 << 4) 82 #define RCC_ENR_GPIO_F_EN (1 << 5) 83 #define RCC_ENR_GPIO_G_EN (1 << 6) 84 #define RCC_ENR_GPIO_H_EN (1 << 7) 85 #define RCC_ENR_GPIO_I_EN (1 << 8) 86 #define RCC_ENR_GPIO_J_EN (1 << 9) 87 #define RCC_ENR_GPIO_K_EN (1 << 10) 88 89 struct pll_psc { 90 u8 pll_m; 91 u16 pll_n; 92 u8 pll_p; 93 u8 pll_q; 94 u8 ahb_psc; 95 u8 apb1_psc; 96 u8 apb2_psc; 97 }; 98 99 #define AHB_PSC_1 0 100 #define AHB_PSC_2 0x8 101 #define AHB_PSC_4 0x9 102 #define AHB_PSC_8 0xA 103 #define AHB_PSC_16 0xB 104 #define AHB_PSC_64 0xC 105 #define AHB_PSC_128 0xD 106 #define AHB_PSC_256 0xE 107 #define AHB_PSC_512 0xF 108 109 #define APB_PSC_1 0 110 #define APB_PSC_2 0x4 111 #define APB_PSC_4 0x5 112 #define APB_PSC_8 0x6 113 #define APB_PSC_16 0x7 114 115 #if !defined(CONFIG_STM32_HSE_HZ) 116 #error "CONFIG_STM32_HSE_HZ not defined!" 117 #else 118 #if (CONFIG_STM32_HSE_HZ == 8000000) 119 #if (CONFIG_SYS_CLK_FREQ == 180000000) 120 /* 180 MHz */ 121 struct pll_psc sys_pll_psc = { 122 .pll_m = 8, 123 .pll_n = 360, 124 .pll_p = 2, 125 .pll_q = 8, 126 .ahb_psc = AHB_PSC_1, 127 .apb1_psc = APB_PSC_4, 128 .apb2_psc = APB_PSC_2 129 }; 130 #else 131 /* default 168 MHz */ 132 struct pll_psc sys_pll_psc = { 133 .pll_m = 8, 134 .pll_n = 336, 135 .pll_p = 2, 136 .pll_q = 7, 137 .ahb_psc = AHB_PSC_1, 138 .apb1_psc = APB_PSC_4, 139 .apb2_psc = APB_PSC_2 140 }; 141 #endif 142 #else 143 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" 144 #endif 145 #endif 146 147 int configure_clocks(void) 148 { 149 /* Reset RCC configuration */ 150 setbits_le32(&STM32_RCC->cr, RCC_CR_HSION); 151 writel(0, &STM32_RCC->cfgr); /* Reset CFGR */ 152 clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON 153 | RCC_CR_PLLON)); 154 writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */ 155 clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP); 156 writel(0, &STM32_RCC->cir); /* Disable all interrupts */ 157 158 /* Configure for HSE+PLL operation */ 159 setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON); 160 while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) 161 ; 162 163 /* Enable high performance mode, System frequency up to 180 MHz */ 164 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); 165 writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr); 166 167 setbits_le32(&STM32_RCC->cfgr, (( 168 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) 169 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) 170 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); 171 172 writel(sys_pll_psc.pll_m 173 | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT) 174 | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) 175 | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT), 176 &STM32_RCC->pllcfgr); 177 setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC); 178 179 setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON); 180 181 while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY)) 182 ; 183 184 /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */ 185 writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN 186 | FLASH_ACR_DCEN, &STM32_FLASH->acr); 187 188 clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); 189 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); 190 191 while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) != 192 RCC_CFGR_SWS_PLL) 193 ; 194 195 return 0; 196 } 197 198 unsigned long clock_get(enum clock clck) 199 { 200 u32 sysclk = 0; 201 u32 shift = 0; 202 /* Prescaler table lookups for clock computation */ 203 u8 ahb_psc_table[16] = { 204 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 205 }; 206 u8 apb_psc_table[8] = { 207 0, 0, 0, 0, 1, 2, 3, 4 208 }; 209 210 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) == 211 RCC_CFGR_SWS_PLL) { 212 u16 pllm, plln, pllp; 213 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); 214 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) 215 >> RCC_PLLCFGR_PLLN_SHIFT); 216 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) 217 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); 218 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; 219 } 220 221 switch (clck) { 222 case CLOCK_CORE: 223 return sysclk; 224 break; 225 case CLOCK_AHB: 226 shift = ahb_psc_table[( 227 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) 228 >> RCC_CFGR_HPRE_SHIFT)]; 229 return sysclk >>= shift; 230 break; 231 case CLOCK_APB1: 232 shift = apb_psc_table[( 233 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK) 234 >> RCC_CFGR_PPRE1_SHIFT)]; 235 return sysclk >>= shift; 236 break; 237 case CLOCK_APB2: 238 shift = apb_psc_table[( 239 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK) 240 >> RCC_CFGR_PPRE2_SHIFT)]; 241 return sysclk >>= shift; 242 break; 243 default: 244 return 0; 245 break; 246 } 247 } 248 249 void clock_setup(int peripheral) 250 { 251 switch (peripheral) { 252 case USART1_CLOCK_CFG: 253 setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN); 254 break; 255 case GPIO_A_CLOCK_CFG: 256 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN); 257 break; 258 case GPIO_B_CLOCK_CFG: 259 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN); 260 break; 261 case GPIO_C_CLOCK_CFG: 262 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN); 263 break; 264 case GPIO_D_CLOCK_CFG: 265 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN); 266 break; 267 case GPIO_E_CLOCK_CFG: 268 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN); 269 break; 270 case GPIO_F_CLOCK_CFG: 271 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN); 272 break; 273 case GPIO_G_CLOCK_CFG: 274 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN); 275 break; 276 case GPIO_H_CLOCK_CFG: 277 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN); 278 break; 279 case GPIO_I_CLOCK_CFG: 280 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN); 281 break; 282 case GPIO_J_CLOCK_CFG: 283 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN); 284 break; 285 case GPIO_K_CLOCK_CFG: 286 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN); 287 break; 288 default: 289 break; 290 } 291 } 292