1 /* 2 * (C) Copyright 2015 3 * Kamil Lulko, <kamil.lulko@gmail.com> 4 * 5 * (C) Copyright 2014 6 * STMicroelectronics 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/io.h> 13 #include <asm/arch/stm32.h> 14 #include <asm/arch/stm32_periph.h> 15 16 #define RCC_CR_HSION (1 << 0) 17 #define RCC_CR_HSEON (1 << 16) 18 #define RCC_CR_HSERDY (1 << 17) 19 #define RCC_CR_HSEBYP (1 << 18) 20 #define RCC_CR_CSSON (1 << 19) 21 #define RCC_CR_PLLON (1 << 24) 22 #define RCC_CR_PLLRDY (1 << 25) 23 24 #define RCC_PLLCFGR_PLLM_MASK 0x3F 25 #define RCC_PLLCFGR_PLLN_MASK 0x7FC0 26 #define RCC_PLLCFGR_PLLP_MASK 0x30000 27 #define RCC_PLLCFGR_PLLQ_MASK 0xF000000 28 #define RCC_PLLCFGR_PLLSRC (1 << 22) 29 #define RCC_PLLCFGR_PLLN_SHIFT 6 30 #define RCC_PLLCFGR_PLLP_SHIFT 16 31 #define RCC_PLLCFGR_PLLQ_SHIFT 24 32 33 #define RCC_CFGR_AHB_PSC_MASK 0xF0 34 #define RCC_CFGR_APB1_PSC_MASK 0x1C00 35 #define RCC_CFGR_APB2_PSC_MASK 0xE000 36 #define RCC_CFGR_SW0 (1 << 0) 37 #define RCC_CFGR_SW1 (1 << 1) 38 #define RCC_CFGR_SW_MASK 0x3 39 #define RCC_CFGR_SW_HSI 0 40 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0 41 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1 42 #define RCC_CFGR_SWS0 (1 << 2) 43 #define RCC_CFGR_SWS1 (1 << 3) 44 #define RCC_CFGR_SWS_MASK 0xC 45 #define RCC_CFGR_SWS_HSI 0 46 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 47 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 48 #define RCC_CFGR_HPRE_SHIFT 4 49 #define RCC_CFGR_PPRE1_SHIFT 10 50 #define RCC_CFGR_PPRE2_SHIFT 13 51 52 #define RCC_APB1ENR_PWREN (1 << 28) 53 54 /* 55 * RCC USART specific definitions 56 */ 57 #define RCC_ENR_USART1EN (1 << 4) 58 #define RCC_ENR_USART2EN (1 << 17) 59 #define RCC_ENR_USART3EN (1 << 18) 60 #define RCC_ENR_USART6EN (1 << 5) 61 62 #define PWR_CR_VOS0 (1 << 14) 63 #define PWR_CR_VOS1 (1 << 15) 64 #define PWR_CR_VOS_MASK 0xC000 65 #define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1) 66 #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1) 67 #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0) 68 69 #define FLASH_ACR_WS(n) n 70 #define FLASH_ACR_PRFTEN (1 << 8) 71 #define FLASH_ACR_ICEN (1 << 9) 72 #define FLASH_ACR_DCEN (1 << 10) 73 74 struct pll_psc { 75 u8 pll_m; 76 u16 pll_n; 77 u8 pll_p; 78 u8 pll_q; 79 u8 ahb_psc; 80 u8 apb1_psc; 81 u8 apb2_psc; 82 }; 83 84 #define AHB_PSC_1 0 85 #define AHB_PSC_2 0x8 86 #define AHB_PSC_4 0x9 87 #define AHB_PSC_8 0xA 88 #define AHB_PSC_16 0xB 89 #define AHB_PSC_64 0xC 90 #define AHB_PSC_128 0xD 91 #define AHB_PSC_256 0xE 92 #define AHB_PSC_512 0xF 93 94 #define APB_PSC_1 0 95 #define APB_PSC_2 0x4 96 #define APB_PSC_4 0x5 97 #define APB_PSC_8 0x6 98 #define APB_PSC_16 0x7 99 100 #if !defined(CONFIG_STM32_HSE_HZ) 101 #error "CONFIG_STM32_HSE_HZ not defined!" 102 #else 103 #if (CONFIG_STM32_HSE_HZ == 8000000) 104 #if (CONFIG_SYS_CLK_FREQ == 180000000) 105 /* 180 MHz */ 106 struct pll_psc sys_pll_psc = { 107 .pll_m = 8, 108 .pll_n = 360, 109 .pll_p = 2, 110 .pll_q = 8, 111 .ahb_psc = AHB_PSC_1, 112 .apb1_psc = APB_PSC_4, 113 .apb2_psc = APB_PSC_2 114 }; 115 #else 116 /* default 168 MHz */ 117 struct pll_psc sys_pll_psc = { 118 .pll_m = 8, 119 .pll_n = 336, 120 .pll_p = 2, 121 .pll_q = 7, 122 .ahb_psc = AHB_PSC_1, 123 .apb1_psc = APB_PSC_4, 124 .apb2_psc = APB_PSC_2 125 }; 126 #endif 127 #else 128 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" 129 #endif 130 #endif 131 132 int configure_clocks(void) 133 { 134 /* Reset RCC configuration */ 135 setbits_le32(&STM32_RCC->cr, RCC_CR_HSION); 136 writel(0, &STM32_RCC->cfgr); /* Reset CFGR */ 137 clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON 138 | RCC_CR_PLLON)); 139 writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */ 140 clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP); 141 writel(0, &STM32_RCC->cir); /* Disable all interrupts */ 142 143 /* Configure for HSE+PLL operation */ 144 setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON); 145 while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) 146 ; 147 148 /* Enable high performance mode, System frequency up to 180 MHz */ 149 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); 150 writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr); 151 152 setbits_le32(&STM32_RCC->cfgr, (( 153 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) 154 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) 155 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); 156 157 writel(sys_pll_psc.pll_m 158 | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT) 159 | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) 160 | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT), 161 &STM32_RCC->pllcfgr); 162 setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC); 163 164 setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON); 165 166 while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY)) 167 ; 168 169 /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */ 170 writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN 171 | FLASH_ACR_DCEN, &STM32_FLASH->acr); 172 173 clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); 174 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); 175 176 while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) != 177 RCC_CFGR_SWS_PLL) 178 ; 179 180 return 0; 181 } 182 183 unsigned long clock_get(enum clock clck) 184 { 185 u32 sysclk = 0; 186 u32 shift = 0; 187 /* Prescaler table lookups for clock computation */ 188 u8 ahb_psc_table[16] = { 189 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 190 }; 191 u8 apb_psc_table[8] = { 192 0, 0, 0, 0, 1, 2, 3, 4 193 }; 194 195 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) == 196 RCC_CFGR_SWS_PLL) { 197 u16 pllm, plln, pllp; 198 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); 199 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) 200 >> RCC_PLLCFGR_PLLN_SHIFT); 201 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) 202 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); 203 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; 204 } 205 206 switch (clck) { 207 case CLOCK_CORE: 208 return sysclk; 209 break; 210 case CLOCK_AHB: 211 shift = ahb_psc_table[( 212 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) 213 >> RCC_CFGR_HPRE_SHIFT)]; 214 return sysclk >>= shift; 215 break; 216 case CLOCK_APB1: 217 shift = apb_psc_table[( 218 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK) 219 >> RCC_CFGR_PPRE1_SHIFT)]; 220 return sysclk >>= shift; 221 break; 222 case CLOCK_APB2: 223 shift = apb_psc_table[( 224 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK) 225 >> RCC_CFGR_PPRE2_SHIFT)]; 226 return sysclk >>= shift; 227 break; 228 default: 229 return 0; 230 break; 231 } 232 } 233 234 void clock_setup(int peripheral) 235 { 236 switch (peripheral) { 237 case USART1_CLOCK_CFG: 238 setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN); 239 break; 240 default: 241 break; 242 } 243 } 244