1 /* 2 * Copyright (C) 2015 Marek Vasut <marex@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <errno.h> 9 #include <asm/arch/sdram.h> 10 /* QTS output file. */ 11 #include <qts/sdram_config.h> 12 13 #include <qts/sequencer_auto_ac_init.h> 14 #include <qts/sequencer_auto_inst_init.h> 15 #include <qts/sequencer_auto.h> 16 #include <qts/sequencer_defines.h> 17 18 static const struct socfpga_sdram_config sdram_config = { 19 .ctrl_cfg = 20 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << 21 SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) | 22 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << 23 SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) | 24 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER << 25 SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) | 26 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << 27 SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) | 28 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << 29 SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) | 30 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << 31 SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) | 32 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << 33 SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) | 34 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << 35 SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) | 36 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << 37 SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB), 38 .dram_timing1 = 39 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << 40 SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) | 41 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << 42 SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) | 43 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << 44 SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) | 45 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << 46 SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) | 47 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << 48 SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) | 49 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << 50 SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB), 51 .dram_timing2 = 52 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << 53 SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) | 54 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << 55 SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) | 56 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << 57 SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) | 58 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << 59 SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) | 60 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << 61 SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB), 62 .dram_timing3 = 63 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << 64 SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) | 65 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << 66 SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) | 67 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << 68 SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) | 69 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << 70 SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) | 71 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << 72 SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB), 73 .dram_timing4 = 74 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << 75 SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) | 76 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << 77 SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB), 78 .lowpwr_timing = 79 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << 80 SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) | 81 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << 82 SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB), 83 .dram_odt = 84 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ << 85 SDR_CTRLGRP_DRAMODT_READ_LSB) | 86 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << 87 SDR_CTRLGRP_DRAMODT_WRITE_LSB), 88 .dram_addrw = 89 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << 90 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | 91 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS << 92 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) | 93 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << 94 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | 95 ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << 96 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB), 97 .dram_if_width = 98 (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << 99 SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB), 100 .dram_dev_width = 101 (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << 102 SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB), 103 .dram_intr = 104 (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << 105 SDR_CTRLGRP_DRAMINTR_INTREN_LSB), 106 .lowpwr_eq = 107 (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK << 108 SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB), 109 .static_cfg = 110 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << 111 SDR_CTRLGRP_STATICCFG_MEMBL_LSB) | 112 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << 113 SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB), 114 .ctrl_width = 115 (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << 116 SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB), 117 .cport_width = 118 (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << 119 SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB), 120 .cport_wmap = 121 (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << 122 SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB), 123 .cport_rmap = 124 (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << 125 SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB), 126 .rfifo_cmap = 127 (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << 128 SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB), 129 .wfifo_cmap = 130 (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << 131 SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB), 132 .cport_rdwr = 133 (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << 134 SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB), 135 .port_cfg = 136 (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << 137 SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB), 138 .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST, 139 .fifo_cfg = 140 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << 141 SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) | 142 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << 143 SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB), 144 .mp_priority = 145 (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << 146 SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB), 147 .mp_weight0 = 148 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << 149 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB), 150 .mp_weight1 = 151 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << 152 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) | 153 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << 154 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB), 155 .mp_weight2 = 156 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << 157 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB), 158 .mp_weight3 = 159 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << 160 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB), 161 .mp_pacing0 = 162 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << 163 SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB), 164 .mp_pacing1 = 165 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << 166 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) | 167 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << 168 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB), 169 .mp_pacing2 = 170 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << 171 SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB), 172 .mp_pacing3 = 173 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << 174 SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB), 175 .mp_threshold0 = 176 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << 177 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB), 178 .mp_threshold1 = 179 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << 180 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB), 181 .mp_threshold2 = 182 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << 183 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB), 184 .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0, 185 }; 186 187 static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { 188 .activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1, 189 .activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1, 190 .activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2, 191 .activate_1 = RW_MGR_ACTIVATE_1, 192 .clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE, 193 .guaranteed_read = RW_MGR_GUARANTEED_READ, 194 .guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT, 195 .guaranteed_write = RW_MGR_GUARANTEED_WRITE, 196 .guaranteed_write_wait0 = RW_MGR_GUARANTEED_WRITE_WAIT0, 197 .guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1, 198 .guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2, 199 .guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3, 200 .idle = RW_MGR_IDLE, 201 .idle_loop1 = RW_MGR_IDLE_LOOP1, 202 .idle_loop2 = RW_MGR_IDLE_LOOP2, 203 .init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0, 204 .init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0, 205 .lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0, 206 .lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA, 207 .lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS, 208 .lfsr_wr_rd_bank_0_nop = RW_MGR_LFSR_WR_RD_BANK_0_NOP, 209 .lfsr_wr_rd_bank_0_wait = RW_MGR_LFSR_WR_RD_BANK_0_WAIT, 210 .lfsr_wr_rd_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_BANK_0_WL_1, 211 .lfsr_wr_rd_dm_bank_0 = RW_MGR_LFSR_WR_RD_DM_BANK_0, 212 .lfsr_wr_rd_dm_bank_0_data = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA, 213 .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS, 214 .lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, 215 .lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, 216 .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1, 217 .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET, 218 .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR, 219 .mrs0_user = RW_MGR_MRS0_USER, 220 .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR, 221 .mrs1 = RW_MGR_MRS1, 222 .mrs1_mirr = RW_MGR_MRS1_MIRR, 223 .mrs2 = RW_MGR_MRS2, 224 .mrs2_mirr = RW_MGR_MRS2_MIRR, 225 .mrs3 = RW_MGR_MRS3, 226 .mrs3_mirr = RW_MGR_MRS3_MIRR, 227 .precharge_all = RW_MGR_PRECHARGE_ALL, 228 .read_b2b = RW_MGR_READ_B2B, 229 .read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1, 230 .read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2, 231 .refresh_all = RW_MGR_REFRESH_ALL, 232 .rreturn = RW_MGR_RETURN, 233 .sgle_read = RW_MGR_SGLE_READ, 234 .zqcl = RW_MGR_ZQCL, 235 236 .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH, 237 .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING, 238 .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH, 239 .mem_data_width = RW_MGR_MEM_DATA_WIDTH, 240 .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS, 241 .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS, 242 .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH, 243 .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH, 244 .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM, 245 .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS, 246 .mem_virtual_groups_per_read_dqs = 247 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS, 248 .mem_virtual_groups_per_write_dqs = 249 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS, 250 }; 251 252 struct socfpga_sdram_io_config io_config = { 253 .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP, 254 .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP, 255 .delay_per_opa_tap = IO_DELAY_PER_OPA_TAP, 256 .dll_chain_length = IO_DLL_CHAIN_LENGTH, 257 .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX, 258 .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX, 259 .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET, 260 .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX, 261 .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX, 262 .dqs_in_reserve = IO_DQS_IN_RESERVE, 263 .dqs_out_reserve = IO_DQS_OUT_RESERVE, 264 .io_in_delay_max = IO_IO_IN_DELAY_MAX, 265 .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX, 266 .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX, 267 .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS, 268 }; 269 270 struct socfpga_sdram_misc_config misc_config = { 271 .afi_rate_ratio = AFI_RATE_RATIO, 272 .calib_lfifo_offset = CALIB_LFIFO_OFFSET, 273 .calib_vfifo_offset = CALIB_VFIFO_OFFSET, 274 .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION, 275 .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH, 276 .read_valid_fifo_size = READ_VALID_FIFO_SIZE, 277 .reg_file_init_seq_signature = REG_FILE_INIT_SEQ_SIGNATURE, 278 .tinit_cntr0_val = TINIT_CNTR0_VAL, 279 .tinit_cntr1_val = TINIT_CNTR1_VAL, 280 .tinit_cntr2_val = TINIT_CNTR2_VAL, 281 .treset_cntr0_val = TRESET_CNTR0_VAL, 282 .treset_cntr1_val = TRESET_CNTR1_VAL, 283 .treset_cntr2_val = TRESET_CNTR2_VAL, 284 }; 285 286 const struct socfpga_sdram_config *socfpga_get_sdram_config(void) 287 { 288 return &sdram_config; 289 } 290 291 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem) 292 { 293 *init = ac_rom_init; 294 *nelem = ARRAY_SIZE(ac_rom_init); 295 } 296 297 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem) 298 { 299 *init = inst_rom_init; 300 *nelem = ARRAY_SIZE(inst_rom_init); 301 } 302 303 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void) 304 { 305 return &rw_mgr_config; 306 } 307 308 const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void) 309 { 310 return &io_config; 311 } 312 313 const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void) 314 { 315 return &misc_config; 316 } 317