xref: /rk3399_rockchip-uboot/arch/arm/mach-socfpga/timer.c (revision 05a217212b41c6342fc1c6be0fe49ce28c9afe40)
1*05a21721SMasahiro Yamada /*
2*05a21721SMasahiro Yamada  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
3*05a21721SMasahiro Yamada  *
4*05a21721SMasahiro Yamada  * SPDX-License-Identifier:	GPL-2.0+
5*05a21721SMasahiro Yamada  */
6*05a21721SMasahiro Yamada 
7*05a21721SMasahiro Yamada #include <common.h>
8*05a21721SMasahiro Yamada #include <asm/io.h>
9*05a21721SMasahiro Yamada #include <asm/arch/timer.h>
10*05a21721SMasahiro Yamada 
11*05a21721SMasahiro Yamada #define TIMER_LOAD_VAL		0xFFFFFFFF
12*05a21721SMasahiro Yamada 
13*05a21721SMasahiro Yamada static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
14*05a21721SMasahiro Yamada 
15*05a21721SMasahiro Yamada /*
16*05a21721SMasahiro Yamada  * Timer initialization
17*05a21721SMasahiro Yamada  */
timer_init(void)18*05a21721SMasahiro Yamada int timer_init(void)
19*05a21721SMasahiro Yamada {
20*05a21721SMasahiro Yamada 	writel(TIMER_LOAD_VAL, &timer_base->load_val);
21*05a21721SMasahiro Yamada 	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
22*05a21721SMasahiro Yamada 	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
23*05a21721SMasahiro Yamada 	return 0;
24*05a21721SMasahiro Yamada }
25