xref: /rk3399_rockchip-uboot/arch/arm/mach-socfpga/system_manager_gen5.c (revision 753a4dde970c2bc9022321f1093e544e3a150f6e)
1*4ddd541dSLey Foon Tan /*
2*4ddd541dSLey Foon Tan  * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
3*4ddd541dSLey Foon Tan  *
4*4ddd541dSLey Foon Tan  * SPDX-License-Identifier:	GPL-2.0+
5*4ddd541dSLey Foon Tan  */
6*4ddd541dSLey Foon Tan 
7*4ddd541dSLey Foon Tan #include <common.h>
8*4ddd541dSLey Foon Tan #include <asm/io.h>
9*4ddd541dSLey Foon Tan #include <asm/arch/system_manager.h>
10*4ddd541dSLey Foon Tan #include <asm/arch/fpga_manager.h>
11*4ddd541dSLey Foon Tan 
12*4ddd541dSLey Foon Tan DECLARE_GLOBAL_DATA_PTR;
13*4ddd541dSLey Foon Tan 
14*4ddd541dSLey Foon Tan static struct socfpga_system_manager *sysmgr_regs =
15*4ddd541dSLey Foon Tan 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
16*4ddd541dSLey Foon Tan 
17*4ddd541dSLey Foon Tan /*
18*4ddd541dSLey Foon Tan  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
19*4ddd541dSLey Foon Tan  * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
20*4ddd541dSLey Foon Tan  * CONFIG_SYSMGR_ISWGRP_HANDOFF.
21*4ddd541dSLey Foon Tan  */
populate_sysmgr_fpgaintf_module(void)22*4ddd541dSLey Foon Tan static void populate_sysmgr_fpgaintf_module(void)
23*4ddd541dSLey Foon Tan {
24*4ddd541dSLey Foon Tan 	u32 handoff_val = 0;
25*4ddd541dSLey Foon Tan 
26*4ddd541dSLey Foon Tan 	/* ISWGRP_HANDOFF_FPGAINTF */
27*4ddd541dSLey Foon Tan 	writel(0, &sysmgr_regs->iswgrp_handoff[2]);
28*4ddd541dSLey Foon Tan 
29*4ddd541dSLey Foon Tan 	/* Enable the signal for those HPS peripherals that use FPGA. */
30*4ddd541dSLey Foon Tan 	if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
31*4ddd541dSLey Foon Tan 		handoff_val |= SYSMGR_FPGAINTF_NAND;
32*4ddd541dSLey Foon Tan 	if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
33*4ddd541dSLey Foon Tan 		handoff_val |= SYSMGR_FPGAINTF_EMAC1;
34*4ddd541dSLey Foon Tan 	if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
35*4ddd541dSLey Foon Tan 		handoff_val |= SYSMGR_FPGAINTF_SDMMC;
36*4ddd541dSLey Foon Tan 	if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
37*4ddd541dSLey Foon Tan 		handoff_val |= SYSMGR_FPGAINTF_EMAC0;
38*4ddd541dSLey Foon Tan 	if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
39*4ddd541dSLey Foon Tan 		handoff_val |= SYSMGR_FPGAINTF_SPIM0;
40*4ddd541dSLey Foon Tan 	if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
41*4ddd541dSLey Foon Tan 		handoff_val |= SYSMGR_FPGAINTF_SPIM1;
42*4ddd541dSLey Foon Tan 
43*4ddd541dSLey Foon Tan 	/* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
44*4ddd541dSLey Foon Tan 	based on pinmux setting */
45*4ddd541dSLey Foon Tan 	setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
46*4ddd541dSLey Foon Tan 
47*4ddd541dSLey Foon Tan 	handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
48*4ddd541dSLey Foon Tan 	if (fpgamgr_test_fpga_ready()) {
49*4ddd541dSLey Foon Tan 		/* Enable the required signals only */
50*4ddd541dSLey Foon Tan 		writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
51*4ddd541dSLey Foon Tan 	}
52*4ddd541dSLey Foon Tan }
53*4ddd541dSLey Foon Tan 
54*4ddd541dSLey Foon Tan /*
55*4ddd541dSLey Foon Tan  * Configure all the pin muxes
56*4ddd541dSLey Foon Tan  */
sysmgr_pinmux_init(void)57*4ddd541dSLey Foon Tan void sysmgr_pinmux_init(void)
58*4ddd541dSLey Foon Tan {
59*4ddd541dSLey Foon Tan 	u32 regs = (u32)&sysmgr_regs->emacio[0];
60*4ddd541dSLey Foon Tan 	const u8 *sys_mgr_init_table;
61*4ddd541dSLey Foon Tan 	unsigned int len;
62*4ddd541dSLey Foon Tan 	int i;
63*4ddd541dSLey Foon Tan 
64*4ddd541dSLey Foon Tan 	sysmgr_get_pinmux_table(&sys_mgr_init_table, &len);
65*4ddd541dSLey Foon Tan 
66*4ddd541dSLey Foon Tan 	for (i = 0; i < len; i++) {
67*4ddd541dSLey Foon Tan 		writel(sys_mgr_init_table[i], regs);
68*4ddd541dSLey Foon Tan 		regs += sizeof(regs);
69*4ddd541dSLey Foon Tan 	}
70*4ddd541dSLey Foon Tan 
71*4ddd541dSLey Foon Tan 	populate_sysmgr_fpgaintf_module();
72*4ddd541dSLey Foon Tan }
73*4ddd541dSLey Foon Tan 
74*4ddd541dSLey Foon Tan /*
75*4ddd541dSLey Foon Tan  * This bit allows the bootrom to configure the IOs after a warm reset.
76*4ddd541dSLey Foon Tan  */
sysmgr_config_warmrstcfgio(int enable)77*4ddd541dSLey Foon Tan void sysmgr_config_warmrstcfgio(int enable)
78*4ddd541dSLey Foon Tan {
79*4ddd541dSLey Foon Tan 	if (enable)
80*4ddd541dSLey Foon Tan 		setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
81*4ddd541dSLey Foon Tan 			     SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
82*4ddd541dSLey Foon Tan 	else
83*4ddd541dSLey Foon Tan 		clrbits_le32(&sysmgr_regs->romcodegrp_ctrl,
84*4ddd541dSLey Foon Tan 			     SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
85*4ddd541dSLey Foon Tan }
86