1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/pl310.h> 10 #include <asm/u-boot.h> 11 #include <asm/utils.h> 12 #include <image.h> 13 #include <asm/arch/reset_manager.h> 14 #include <spl.h> 15 #include <asm/arch/system_manager.h> 16 #include <asm/arch/freeze_controller.h> 17 #include <asm/arch/clock_manager.h> 18 #include <asm/arch/scan_manager.h> 19 #include <asm/arch/sdram.h> 20 #include <asm/arch/scu.h> 21 #include <asm/arch/nic301.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 static struct pl310_regs *const pl310 = 26 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 27 static struct scu_registers *scu_regs = 28 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 29 static struct nic301_registers *nic301_regs = 30 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 31 32 u32 spl_boot_device(void) 33 { 34 #ifdef CONFIG_SPL_MMC_SUPPORT 35 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); 36 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); 37 return BOOT_DEVICE_MMC1; 38 #else 39 return BOOT_DEVICE_RAM; 40 #endif 41 } 42 43 #ifdef CONFIG_SPL_MMC_SUPPORT 44 u32 spl_boot_mode(void) 45 { 46 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 47 return MMCSD_MODE_FS; 48 #else 49 return MMCSD_MODE_RAW; 50 #endif 51 } 52 #endif 53 54 static void socfpga_nic301_slave_ns(void) 55 { 56 writel(0x1, &nic301_regs->lwhps2fpgaregs); 57 writel(0x1, &nic301_regs->hps2fpgaregs); 58 writel(0x1, &nic301_regs->acp); 59 writel(0x1, &nic301_regs->rom); 60 writel(0x1, &nic301_regs->ocram); 61 writel(0x1, &nic301_regs->sdrdata); 62 } 63 64 void board_init_f(ulong dummy) 65 { 66 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET 67 const struct cm_config *cm_default_cfg = cm_get_default_config(); 68 #endif 69 struct socfpga_system_manager *sysmgr_regs = 70 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 71 unsigned long sdram_size; 72 unsigned long reg; 73 74 /* 75 * First C code to run. Clear fake OCRAM ECC first as SBE 76 * and DBE might triggered during power on 77 */ 78 reg = readl(&sysmgr_regs->eccgrp_ocram); 79 if (reg & SYSMGR_ECC_OCRAM_SERR) 80 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, 81 &sysmgr_regs->eccgrp_ocram); 82 if (reg & SYSMGR_ECC_OCRAM_DERR) 83 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, 84 &sysmgr_regs->eccgrp_ocram); 85 86 memset(__bss_start, 0, __bss_end - __bss_start); 87 88 socfpga_nic301_slave_ns(); 89 90 /* Configure ARM MPU SNSAC register. */ 91 setbits_le32(&scu_regs->sacr, 0xfff); 92 93 /* Remap SDRAM to 0x0 */ 94 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 95 writel(0x1, &pl310->pl310_addr_filter_start); 96 97 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET 98 debug("Freezing all I/O banks\n"); 99 /* freeze all IO banks */ 100 sys_mgr_frzctrl_freeze_req(); 101 102 /* Put everything into reset but L4WD0. */ 103 socfpga_per_reset_all(); 104 /* Put FPGA bridges into reset too. */ 105 socfpga_bridges_reset(1); 106 107 socfpga_per_reset(SOCFPGA_RESET(SDR), 0); 108 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); 109 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); 110 111 timer_init(); 112 113 debug("Reconfigure Clock Manager\n"); 114 /* reconfigure the PLLs */ 115 cm_basic_init(cm_default_cfg); 116 117 /* Enable bootrom to configure IOs. */ 118 sysmgr_config_warmrstcfgio(1); 119 120 /* configure the IOCSR / IO buffer settings */ 121 if (scan_mgr_configure_iocsr()) 122 hang(); 123 124 sysmgr_config_warmrstcfgio(0); 125 126 /* configure the pin muxing through system manager */ 127 sysmgr_config_warmrstcfgio(1); 128 sysmgr_pinmux_init(); 129 sysmgr_config_warmrstcfgio(0); 130 131 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ 132 133 /* De-assert reset for peripherals and bridges based on handoff */ 134 reset_deassert_peripherals_handoff(); 135 socfpga_bridges_reset(0); 136 137 debug("Unfreezing/Thaw all I/O banks\n"); 138 /* unfreeze / thaw all IO banks */ 139 sys_mgr_frzctrl_thaw_req(); 140 141 /* enable console uart printing */ 142 preloader_console_init(); 143 144 if (sdram_mmr_init_full(0xffffffff) != 0) { 145 puts("SDRAM init failed.\n"); 146 hang(); 147 } 148 149 debug("SDRAM: Calibrating PHY\n"); 150 /* SDRAM calibration */ 151 if (sdram_calibration_full() == 0) { 152 puts("SDRAM calibration failed.\n"); 153 hang(); 154 } 155 156 sdram_size = sdram_calculate_size(); 157 debug("SDRAM: %ld MiB\n", sdram_size >> 20); 158 159 /* Sanity check ensure correct SDRAM size specified */ 160 if (get_ram_size(0, sdram_size) != sdram_size) { 161 puts("SDRAM size check failed!\n"); 162 hang(); 163 } 164 165 socfpga_bridges_reset(1); 166 167 board_init_r(NULL, 0); 168 } 169