1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/pl310.h> 10 #include <asm/u-boot.h> 11 #include <asm/utils.h> 12 #include <image.h> 13 #include <asm/arch/reset_manager.h> 14 #include <spl.h> 15 #include <asm/arch/system_manager.h> 16 #include <asm/arch/freeze_controller.h> 17 #include <asm/arch/clock_manager.h> 18 #include <asm/arch/scan_manager.h> 19 #include <asm/arch/sdram.h> 20 #include <asm/arch/scu.h> 21 #include <asm/arch/nic301.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 static struct pl310_regs *const pl310 = 26 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 27 static struct scu_registers *scu_regs = 28 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 29 static struct nic301_registers *nic301_regs = 30 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 31 static struct socfpga_system_manager *sysmgr_regs = 32 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 33 34 u32 spl_boot_device(void) 35 { 36 const u32 bsel = readl(&sysmgr_regs->bootinfo); 37 38 switch (bsel & 0x7) { 39 case 0x1: /* FPGA (HPS2FPGA Bridge) */ 40 return BOOT_DEVICE_RAM; 41 case 0x2: /* NAND Flash (1.8V) */ 42 case 0x3: /* NAND Flash (3.0V) */ 43 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); 44 return BOOT_DEVICE_NAND; 45 case 0x4: /* SD/MMC External Transceiver (1.8V) */ 46 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ 47 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); 48 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); 49 return BOOT_DEVICE_MMC1; 50 case 0x6: /* QSPI Flash (1.8V) */ 51 case 0x7: /* QSPI Flash (3.0V) */ 52 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); 53 return BOOT_DEVICE_SPI; 54 default: 55 printf("Invalid boot device (bsel=%08x)!\n", bsel); 56 hang(); 57 } 58 } 59 60 #ifdef CONFIG_SPL_MMC_SUPPORT 61 u32 spl_boot_mode(const u32 boot_device) 62 { 63 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 64 return MMCSD_MODE_FS; 65 #else 66 return MMCSD_MODE_RAW; 67 #endif 68 } 69 #endif 70 71 static void socfpga_nic301_slave_ns(void) 72 { 73 writel(0x1, &nic301_regs->lwhps2fpgaregs); 74 writel(0x1, &nic301_regs->hps2fpgaregs); 75 writel(0x1, &nic301_regs->acp); 76 writel(0x1, &nic301_regs->rom); 77 writel(0x1, &nic301_regs->ocram); 78 writel(0x1, &nic301_regs->sdrdata); 79 } 80 81 void board_init_f(ulong dummy) 82 { 83 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET 84 const struct cm_config *cm_default_cfg = cm_get_default_config(); 85 #endif 86 unsigned long sdram_size; 87 unsigned long reg; 88 89 /* 90 * First C code to run. Clear fake OCRAM ECC first as SBE 91 * and DBE might triggered during power on 92 */ 93 reg = readl(&sysmgr_regs->eccgrp_ocram); 94 if (reg & SYSMGR_ECC_OCRAM_SERR) 95 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, 96 &sysmgr_regs->eccgrp_ocram); 97 if (reg & SYSMGR_ECC_OCRAM_DERR) 98 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, 99 &sysmgr_regs->eccgrp_ocram); 100 101 memset(__bss_start, 0, __bss_end - __bss_start); 102 103 socfpga_nic301_slave_ns(); 104 105 /* Configure ARM MPU SNSAC register. */ 106 setbits_le32(&scu_regs->sacr, 0xfff); 107 108 /* Remap SDRAM to 0x0 */ 109 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 110 writel(0x1, &pl310->pl310_addr_filter_start); 111 112 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET 113 debug("Freezing all I/O banks\n"); 114 /* freeze all IO banks */ 115 sys_mgr_frzctrl_freeze_req(); 116 117 /* Put everything into reset but L4WD0. */ 118 socfpga_per_reset_all(); 119 /* Put FPGA bridges into reset too. */ 120 socfpga_bridges_reset(1); 121 122 socfpga_per_reset(SOCFPGA_RESET(SDR), 0); 123 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); 124 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); 125 126 timer_init(); 127 128 debug("Reconfigure Clock Manager\n"); 129 /* reconfigure the PLLs */ 130 cm_basic_init(cm_default_cfg); 131 132 /* Enable bootrom to configure IOs. */ 133 sysmgr_config_warmrstcfgio(1); 134 135 /* configure the IOCSR / IO buffer settings */ 136 if (scan_mgr_configure_iocsr()) 137 hang(); 138 139 sysmgr_config_warmrstcfgio(0); 140 141 /* configure the pin muxing through system manager */ 142 sysmgr_config_warmrstcfgio(1); 143 sysmgr_pinmux_init(); 144 sysmgr_config_warmrstcfgio(0); 145 146 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ 147 148 /* De-assert reset for peripherals and bridges based on handoff */ 149 reset_deassert_peripherals_handoff(); 150 socfpga_bridges_reset(0); 151 152 debug("Unfreezing/Thaw all I/O banks\n"); 153 /* unfreeze / thaw all IO banks */ 154 sys_mgr_frzctrl_thaw_req(); 155 156 /* enable console uart printing */ 157 preloader_console_init(); 158 159 if (sdram_mmr_init_full(0xffffffff) != 0) { 160 puts("SDRAM init failed.\n"); 161 hang(); 162 } 163 164 debug("SDRAM: Calibrating PHY\n"); 165 /* SDRAM calibration */ 166 if (sdram_calibration_full() == 0) { 167 puts("SDRAM calibration failed.\n"); 168 hang(); 169 } 170 171 sdram_size = sdram_calculate_size(); 172 debug("SDRAM: %ld MiB\n", sdram_size >> 20); 173 174 /* Sanity check ensure correct SDRAM size specified */ 175 if (get_ram_size(0, sdram_size) != sdram_size) { 176 puts("SDRAM size check failed!\n"); 177 hang(); 178 } 179 180 socfpga_bridges_reset(1); 181 182 /* Configure simple malloc base pointer into RAM. */ 183 gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); 184 } 185