130088b09SMasahiro Yamada /* 24ddd541dSLey Foon Tan * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 330088b09SMasahiro Yamada * 430088b09SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 530088b09SMasahiro Yamada */ 630088b09SMasahiro Yamada 730088b09SMasahiro Yamada #ifndef _SYSTEM_MANAGER_H_ 830088b09SMasahiro Yamada #define _SYSTEM_MANAGER_H_ 930088b09SMasahiro Yamada 10*86f032e6SLey Foon Tan #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) 11*86f032e6SLey Foon Tan #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) 12*86f032e6SLey Foon Tan #define SYSMGR_ECC_OCRAM_EN BIT(0) 13*86f032e6SLey Foon Tan #define SYSMGR_ECC_OCRAM_SERR BIT(3) 14*86f032e6SLey Foon Tan #define SYSMGR_ECC_OCRAM_DERR BIT(4) 1530088b09SMasahiro Yamada #define SYSMGR_FPGAINTF_USEFPGA 0x1 16*86f032e6SLey Foon Tan #define SYSMGR_FPGAINTF_SPIM0 BIT(0) 17*86f032e6SLey Foon Tan #define SYSMGR_FPGAINTF_SPIM1 BIT(1) 18*86f032e6SLey Foon Tan #define SYSMGR_FPGAINTF_EMAC0 BIT(2) 19*86f032e6SLey Foon Tan #define SYSMGR_FPGAINTF_EMAC1 BIT(3) 20*86f032e6SLey Foon Tan #define SYSMGR_FPGAINTF_NAND BIT(4) 21*86f032e6SLey Foon Tan #define SYSMGR_FPGAINTF_SDMMC BIT(5) 2230088b09SMasahiro Yamada 23a1684b61SDinh Nguyen #define SYSMGR_SDMMC_DRVSEL_SHIFT 0 2430088b09SMasahiro Yamada 2530088b09SMasahiro Yamada /* EMAC Group Bit definitions */ 2630088b09SMasahiro Yamada #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 2730088b09SMasahiro Yamada #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 2830088b09SMasahiro Yamada #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 2930088b09SMasahiro Yamada 3030088b09SMasahiro Yamada #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 3130088b09SMasahiro Yamada #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 3230088b09SMasahiro Yamada #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 3330088b09SMasahiro Yamada 34*86f032e6SLey Foon Tan /* For dedicated IO configuration */ 35*86f032e6SLey Foon Tan /* Voltage select enums */ 36*86f032e6SLey Foon Tan #define VOLTAGE_SEL_3V 0x0 37*86f032e6SLey Foon Tan #define VOLTAGE_SEL_1P8V 0x1 38*86f032e6SLey Foon Tan #define VOLTAGE_SEL_2P5V 0x2 39*86f032e6SLey Foon Tan 40*86f032e6SLey Foon Tan /* Input buffer enable */ 41*86f032e6SLey Foon Tan #define INPUT_BUF_DISABLE 0 42*86f032e6SLey Foon Tan #define INPUT_BUF_1P8V 1 43*86f032e6SLey Foon Tan #define INPUT_BUF_2P5V3V 2 44*86f032e6SLey Foon Tan 45*86f032e6SLey Foon Tan /* Weak pull up enable */ 46*86f032e6SLey Foon Tan #define WK_PU_DISABLE 0 47*86f032e6SLey Foon Tan #define WK_PU_ENABLE 1 48*86f032e6SLey Foon Tan 49*86f032e6SLey Foon Tan /* Pull up slew rate control */ 50*86f032e6SLey Foon Tan #define PU_SLW_RT_SLOW 0 51*86f032e6SLey Foon Tan #define PU_SLW_RT_FAST 1 52*86f032e6SLey Foon Tan #define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW 53*86f032e6SLey Foon Tan 54*86f032e6SLey Foon Tan /* Pull down slew rate control */ 55*86f032e6SLey Foon Tan #define PD_SLW_RT_SLOW 0 56*86f032e6SLey Foon Tan #define PD_SLW_RT_FAST 1 57*86f032e6SLey Foon Tan #define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW 58*86f032e6SLey Foon Tan 59*86f032e6SLey Foon Tan /* Drive strength control */ 60*86f032e6SLey Foon Tan #define PU_DRV_STRG_DEFAULT 0x10 61*86f032e6SLey Foon Tan #define PD_DRV_STRG_DEFAULT 0x10 62*86f032e6SLey Foon Tan 63*86f032e6SLey Foon Tan /* bit position */ 64*86f032e6SLey Foon Tan #define PD_DRV_STRG_LSB 0 65*86f032e6SLey Foon Tan #define PD_SLW_RT_LSB 5 66*86f032e6SLey Foon Tan #define PU_DRV_STRG_LSB 8 67*86f032e6SLey Foon Tan #define PU_SLW_RT_LSB 13 68*86f032e6SLey Foon Tan #define WK_PU_LSB 16 69*86f032e6SLey Foon Tan #define INPUT_BUF_LSB 17 70*86f032e6SLey Foon Tan #define BIAS_TRIM_LSB 19 71*86f032e6SLey Foon Tan #define VOLTAGE_SEL_LSB 0 72*86f032e6SLey Foon Tan 73*86f032e6SLey Foon Tan #define ALT_SYSMGR_NOC_H2F_SET_MSK BIT(0) 74*86f032e6SLey Foon Tan #define ALT_SYSMGR_NOC_LWH2F_SET_MSK BIT(4) 75*86f032e6SLey Foon Tan #define ALT_SYSMGR_NOC_F2H_SET_MSK BIT(8) 76*86f032e6SLey Foon Tan #define ALT_SYSMGR_NOC_F2SDR0_SET_MSK BIT(16) 77*86f032e6SLey Foon Tan #define ALT_SYSMGR_NOC_F2SDR1_SET_MSK BIT(20) 78*86f032e6SLey Foon Tan #define ALT_SYSMGR_NOC_F2SDR2_SET_MSK BIT(24) 79*86f032e6SLey Foon Tan #define ALT_SYSMGR_NOC_TMO_EN_SET_MSK BIT(0) 80*86f032e6SLey Foon Tan 81*86f032e6SLey Foon Tan #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK BIT(1) 82*86f032e6SLey Foon Tan #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK BIT(1) 83*86f032e6SLey Foon Tan 844ddd541dSLey Foon Tan #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 854ddd541dSLey Foon Tan #include <asm/arch/system_manager_gen5.h> 86*86f032e6SLey Foon Tan #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 87*86f032e6SLey Foon Tan #include <asm/arch/system_manager_arria10.h> 884ddd541dSLey Foon Tan #endif 894ddd541dSLey Foon Tan 904ddd541dSLey Foon Tan #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \ 914ddd541dSLey Foon Tan (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7) 924ddd541dSLey Foon Tan 9330088b09SMasahiro Yamada #endif /* _SYSTEM_MANAGER_H_ */ 94