1*2b09ea48SLey Foon Tan /* 2*2b09ea48SLey Foon Tan * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 3*2b09ea48SLey Foon Tan * 4*2b09ea48SLey Foon Tan * SPDX-License-Identifier: GPL-2.0+ 5*2b09ea48SLey Foon Tan */ 6*2b09ea48SLey Foon Tan 7*2b09ea48SLey Foon Tan #ifndef _RESET_MANAGER_GEN5_H_ 8*2b09ea48SLey Foon Tan #define _RESET_MANAGER_GEN5_H_ 9*2b09ea48SLey Foon Tan 10*2b09ea48SLey Foon Tan #include <dt-bindings/reset/altr,rst-mgr.h> 11*2b09ea48SLey Foon Tan 12*2b09ea48SLey Foon Tan void reset_deassert_peripherals_handoff(void); 13*2b09ea48SLey Foon Tan void socfpga_bridges_reset(int enable); 14*2b09ea48SLey Foon Tan 15*2b09ea48SLey Foon Tan struct socfpga_reset_manager { 16*2b09ea48SLey Foon Tan u32 status; 17*2b09ea48SLey Foon Tan u32 ctrl; 18*2b09ea48SLey Foon Tan u32 counts; 19*2b09ea48SLey Foon Tan u32 padding1; 20*2b09ea48SLey Foon Tan u32 mpu_mod_reset; 21*2b09ea48SLey Foon Tan u32 per_mod_reset; 22*2b09ea48SLey Foon Tan u32 per2_mod_reset; 23*2b09ea48SLey Foon Tan u32 brg_mod_reset; 24*2b09ea48SLey Foon Tan u32 misc_mod_reset; 25*2b09ea48SLey Foon Tan u32 padding2[12]; 26*2b09ea48SLey Foon Tan u32 tstscratch; 27*2b09ea48SLey Foon Tan }; 28*2b09ea48SLey Foon Tan 29*2b09ea48SLey Foon Tan /* 30*2b09ea48SLey Foon Tan * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: 31*2b09ea48SLey Foon Tan * 0 ... mpumodrst 32*2b09ea48SLey Foon Tan * 1 ... permodrst 33*2b09ea48SLey Foon Tan * 2 ... per2modrst 34*2b09ea48SLey Foon Tan * 3 ... brgmodrst 35*2b09ea48SLey Foon Tan * 4 ... miscmodrst 36*2b09ea48SLey Foon Tan */ 37*2b09ea48SLey Foon Tan #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) 38*2b09ea48SLey Foon Tan #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) 39*2b09ea48SLey Foon Tan #define RSTMGR_NAND RSTMGR_DEFINE(1, 4) 40*2b09ea48SLey Foon Tan #define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) 41*2b09ea48SLey Foon Tan #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) 42*2b09ea48SLey Foon Tan #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) 43*2b09ea48SLey Foon Tan #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) 44*2b09ea48SLey Foon Tan #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) 45*2b09ea48SLey Foon Tan #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) 46*2b09ea48SLey Foon Tan #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) 47*2b09ea48SLey Foon Tan #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) 48*2b09ea48SLey Foon Tan #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) 49*2b09ea48SLey Foon Tan 50*2b09ea48SLey Foon Tan #endif /* _RESET_MANAGER_GEN5_H_ */ 51