130088b09SMasahiro Yamada /* 26867e19aSTien Fong Chee * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 330088b09SMasahiro Yamada * All rights reserved. 430088b09SMasahiro Yamada * 530088b09SMasahiro Yamada * SPDX-License-Identifier: BSD-3-Clause 630088b09SMasahiro Yamada */ 730088b09SMasahiro Yamada 830088b09SMasahiro Yamada #ifndef _FPGA_MANAGER_H_ 930088b09SMasahiro Yamada #define _FPGA_MANAGER_H_ 1030088b09SMasahiro Yamada 1130088b09SMasahiro Yamada #include <altera.h> 1230088b09SMasahiro Yamada 136867e19aSTien Fong Chee #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 146867e19aSTien Fong Chee #include <asm/arch/fpga_manager_gen5.h> 15*2baa9972STien Fong Chee #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 16*2baa9972STien Fong Chee #include <asm/arch/fpga_manager_arria10.h> 176867e19aSTien Fong Chee #endif 1830088b09SMasahiro Yamada 1930088b09SMasahiro Yamada /* FPGA CD Ratio Value */ 2030088b09SMasahiro Yamada #define CDRATIO_x1 0x0 2130088b09SMasahiro Yamada #define CDRATIO_x2 0x1 2230088b09SMasahiro Yamada #define CDRATIO_x4 0x2 2330088b09SMasahiro Yamada #define CDRATIO_x8 0x3 2430088b09SMasahiro Yamada 256867e19aSTien Fong Chee #ifndef __ASSEMBLY__ 2630088b09SMasahiro Yamada 276867e19aSTien Fong Chee /* Common prototypes */ 286867e19aSTien Fong Chee int fpgamgr_get_mode(void); 296867e19aSTien Fong Chee int fpgamgr_poll_fpga_ready(void); 306867e19aSTien Fong Chee void fpgamgr_program_write(const void *rbf_data, size_t rbf_size); 316867e19aSTien Fong Chee int fpgamgr_test_fpga_ready(void); 326867e19aSTien Fong Chee int fpgamgr_dclkcnt_set(unsigned long cnt); 336867e19aSTien Fong Chee 346867e19aSTien Fong Chee #endif /* __ASSEMBLY__ */ 3530088b09SMasahiro Yamada #endif /* _FPGA_MANAGER_H_ */ 36