xref: /rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/include/mach/pwm.h (revision a71d99ac03c8d5d9622962344485b04aade27b67)
1*225f5eecSMinkyu Kang /*
2*225f5eecSMinkyu Kang  * Copyright (C) 2009 Samsung Electronics
3*225f5eecSMinkyu Kang  * Kyungmin Park <kyungmin.park@samsung.com>
4*225f5eecSMinkyu Kang  * Minkyu Kang <mk7.kang@samsung.com>
5*225f5eecSMinkyu Kang  *
6*225f5eecSMinkyu Kang  * SPDX-License-Identifier:	GPL-2.0+
7*225f5eecSMinkyu Kang  */
8*225f5eecSMinkyu Kang 
9*225f5eecSMinkyu Kang #ifndef __ASM_ARM_ARCH_PWM_H_
10*225f5eecSMinkyu Kang #define __ASM_ARM_ARCH_PWM_H_
11*225f5eecSMinkyu Kang 
12*225f5eecSMinkyu Kang #define PRESCALER_0		(8 - 1)		/* prescaler of timer 0, 1 */
13*225f5eecSMinkyu Kang #define PRESCALER_1		(16 - 1)	/* prescaler of timer 2, 3, 4 */
14*225f5eecSMinkyu Kang 
15*225f5eecSMinkyu Kang /* Divider MUX */
16*225f5eecSMinkyu Kang #define MUX_DIV_1		0		/* 1/1 period */
17*225f5eecSMinkyu Kang #define MUX_DIV_2		1		/* 1/2 period */
18*225f5eecSMinkyu Kang #define MUX_DIV_4		2		/* 1/4 period */
19*225f5eecSMinkyu Kang #define MUX_DIV_8		3		/* 1/8 period */
20*225f5eecSMinkyu Kang #define MUX_DIV_16		4		/* 1/16 period */
21*225f5eecSMinkyu Kang 
22*225f5eecSMinkyu Kang #define MUX_DIV_SHIFT(x)	(x * 4)
23*225f5eecSMinkyu Kang 
24*225f5eecSMinkyu Kang #define TCON_OFFSET(x)		((x + 1) * (!!x) << 2)
25*225f5eecSMinkyu Kang 
26*225f5eecSMinkyu Kang #define TCON_START(x)		(1 << TCON_OFFSET(x))
27*225f5eecSMinkyu Kang #define TCON_UPDATE(x)		(1 << (TCON_OFFSET(x) + 1))
28*225f5eecSMinkyu Kang #define TCON_INVERTER(x)	(1 << (TCON_OFFSET(x) + 2))
29*225f5eecSMinkyu Kang #define TCON_AUTO_RELOAD(x)	(1 << (TCON_OFFSET(x) + 3))
30*225f5eecSMinkyu Kang #define TCON4_AUTO_RELOAD	(1 << 22)
31*225f5eecSMinkyu Kang 
32*225f5eecSMinkyu Kang #ifndef __ASSEMBLY__
33*225f5eecSMinkyu Kang struct s5p_timer {
34*225f5eecSMinkyu Kang 	unsigned int	tcfg0;
35*225f5eecSMinkyu Kang 	unsigned int	tcfg1;
36*225f5eecSMinkyu Kang 	unsigned int	tcon;
37*225f5eecSMinkyu Kang 	unsigned int	tcntb0;
38*225f5eecSMinkyu Kang 	unsigned int	tcmpb0;
39*225f5eecSMinkyu Kang 	unsigned int	tcnto0;
40*225f5eecSMinkyu Kang 	unsigned int	tcntb1;
41*225f5eecSMinkyu Kang 	unsigned int	tcmpb1;
42*225f5eecSMinkyu Kang 	unsigned int	tcnto1;
43*225f5eecSMinkyu Kang 	unsigned int	tcntb2;
44*225f5eecSMinkyu Kang 	unsigned int	tcmpb2;
45*225f5eecSMinkyu Kang 	unsigned int	tcnto2;
46*225f5eecSMinkyu Kang 	unsigned int	tcntb3;
47*225f5eecSMinkyu Kang 	unsigned int	res1;
48*225f5eecSMinkyu Kang 	unsigned int	tcnto3;
49*225f5eecSMinkyu Kang 	unsigned int	tcntb4;
50*225f5eecSMinkyu Kang 	unsigned int	tcnto4;
51*225f5eecSMinkyu Kang 	unsigned int	tintcstat;
52*225f5eecSMinkyu Kang };
53*225f5eecSMinkyu Kang #endif	/* __ASSEMBLY__ */
54*225f5eecSMinkyu Kang 
55*225f5eecSMinkyu Kang #endif
56