1 /* 2 * Copyright (c) 2023 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <boot_rkimg.h> 8 #include <dm.h> 9 #include <fdt_support.h> 10 #include <misc.h> 11 #include <mmc.h> 12 #include <scsi.h> 13 #include <spl.h> 14 #include <asm/io.h> 15 #include <asm/arch/bootrom.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/boot_mode.h> 19 #include <asm/arch/ioc_rk3576.h> 20 #include <asm/arch/rockchip_smccc.h> 21 #include <asm/system.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define SYS_GRF_BASE 0x2600A000 26 #define SYS_GRF_SOC_CON2 0x0008 27 #define SYS_GRF_SOC_CON7 0x001c 28 #define SYS_GRF_SOC_CON11 0x002c 29 #define SYS_GRF_SOC_CON12 0x0030 30 31 #define GPIO0_IOC_BASE 0x26040000 32 #define GPIO0B_PULL_L 0x0024 33 #define GPIO0B_IE_L 0x002C 34 35 #define TOP_IOC_BASE 0x26044000 36 #define GPIO1A_IOMUX_SEL_L 0x0020 37 #define GPIO1A_IOMUX_SEL_H 0x0024 38 #define GPIO1B_IOMUX_SEL_L 0x0028 39 #define GPIO1B_IOMUX_SEL_H 0x002c 40 #define GPIO1C_IOMUX_SEL_L 0x0030 41 #define GPIO1C_IOMUX_SEL_H 0x0034 42 #define GPIO1D_IOMUX_SEL_L 0x0038 43 #define GPIO1D_IOMUX_SEL_H 0x003c 44 #define GPIO2A_IOMUX_SEL_L 0x0040 45 #define GPIO2A_IOMUX_SEL_H 0x0044 46 47 #define VCCIO_IOC_BASE 0x26046000 48 #define VCCIO_IOC_GPIO1C_PUL 0x118 49 #define VCCIO_IOC_GPIO1D_PUL 0x11C 50 #define VCCIO_IOC_GPIO2A_PUL 0x120 51 52 #define VCCIO6_IOC_BASE 0x2604a000 53 #define VCCIO7_IOC_BASE 0x2604b000 54 #define VCCIO7_IOC_GPIO4D_IOMUX_SEL_L 0x0398 55 #define VCCIO7_IOC_XIN_UFS_CON 0x0400 56 57 #define PMU1_SGRF_BASE 0x26002000 58 #define PMU1_SGRF_SOC_CON10 0x0028 59 #define PMU1_SGRF_SOC_CON11 0x002C 60 61 #define SYS_SGRF_BASE 0x26004000 62 #define SYS_SGRF_SOC_CON14 0x0058 63 #define SYS_SGRF_SOC_CON15 0x005C 64 #define SYS_SGRF_SOC_CON20 0x0070 65 66 #define FW_SYS_SGRF_BASE 0x26005000 67 #define SGRF_DOMAIN_CON1 0x4 68 #define SGRF_DOMAIN_CON2 0x8 69 #define SGRF_DOMAIN_CON3 0xc 70 #define SGRF_DOMAIN_CON4 0x10 71 #define SGRF_DOMAIN_CON5 0x14 72 73 #define USBGRF_BASE 0x2601e000 74 #define USB_GRF_USB3OTG0_CON1 0x0030 75 76 #define PMU1_GRF_BASE 0x26026000 77 #define OS_REG0 0x200 78 #define USB2PHY0_GRF_BASE 0x2602e000 79 #define USB2PHY1_GRF_BASE 0x26030000 80 #define USB2PHY_GRF_CON4 0x0010 81 #define USB2PHY_GRF_DBG_CON 0x0040 82 #define USB2PHY_GRF_LS_TIMEOUT 0x0044 83 #define USB2PHY_GRF_LS_DEB 0x0048 84 #define USB2PHY_GRF_RX_TIMEOUT 0x004c 85 #define USB2PHY_GRF_SEQ_LIMT 0x0050 86 87 #define TOP_CRU_BASE 0x27200000 88 #define TOP_CRU_GATE_CON19 0x084C 89 #define TOP_CRU_SOFTRST_CON19 0x0a4C 90 #define PHPPHYSOFTRST_CON01 0x8a04 91 92 #define PMU1_CRU_BASE 0x27220000 93 #define PMU1_CRU_CLKSEL_CON03 0x030c 94 #define PMU1_CRU_GATE_CON03 0x080C 95 #define PMU1_CRU_SOFTRST_CON03 0x0a0C 96 97 #define SATA0_BASE_ADDR 0x2a240000 98 #define SATA1_BASE_ADDR 0x2a250000 99 #define SATA_PI 0xC 100 #define SATA_PORT_CMD 0x118 101 #define SATA_FBS_ENABLE BIT(22) 102 103 #ifdef CONFIG_ARM64 104 #include <asm/armv8/mmu.h> 105 106 static struct mm_region rk3576_mem_map[] = { 107 { 108 .virt = 0x20000000UL, 109 .phys = 0x20000000UL, 110 .size = 0xb080000UL, 111 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 112 PTE_BLOCK_NON_SHARE | 113 PTE_BLOCK_PXN | PTE_BLOCK_UXN 114 }, { 115 .virt = 0x3fe70000UL, 116 .phys = 0x3fe70000UL, 117 .size = 0x190000UL, 118 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 119 PTE_BLOCK_NON_SHARE | 120 PTE_BLOCK_PXN | PTE_BLOCK_UXN 121 }, { 122 .virt = 0x40000000UL, 123 .phys = 0x40000000UL, 124 .size = 0x100000000UL - 0x40000000UL, 125 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 126 PTE_BLOCK_INNER_SHARE 127 }, { 128 .virt = 0x100000000UL, 129 .phys = 0x100000000UL, 130 .size = 0x400000000UL, 131 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 132 PTE_BLOCK_INNER_SHARE 133 }, { 134 .virt = 0x900000000UL, 135 .phys = 0x900000000UL, 136 .size = 0x100800000UL, 137 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 138 PTE_BLOCK_NON_SHARE | 139 PTE_BLOCK_PXN | PTE_BLOCK_UXN 140 }, { 141 /* List terminator */ 142 0, 143 } 144 }; 145 146 struct mm_region *mem_map = rk3576_mem_map; 147 #endif 148 149 void board_debug_uart_init(void) 150 { 151 } 152 153 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 154 [BROM_BOOTSOURCE_EMMC] = "/mmc@2a330000", 155 [BROM_BOOTSOURCE_SD] = "/mmc@2a310000", 156 [BROM_BOOTSOURCE_UFS] = "/ufs@2a2d0000", 157 }; 158 159 #ifdef CONFIG_SPL_BUILD 160 void rockchip_stimer_init(void) 161 { 162 u32 reg; 163 164 /* If Timer already enabled, don't re-init it */ 165 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4); 166 if (reg & 0x1) 167 return; 168 #ifdef COUNTER_FREQUENCY 169 asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY)); 170 #endif 171 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14); 172 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18); 173 writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x04); 174 } 175 #endif 176 177 void reset_misc(void) 178 { 179 #ifdef CONFIG_SPL_BUILD 180 /* For RK3576 SPL, should extraly write os_reg0 and reset to maskrom. */ 181 if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) == BOOT_BROM_DOWNLOAD) 182 writel(BOOT_BROM_DOWNLOAD, PMU1_GRF_BASE + OS_REG0); 183 #elif CONFIG_SUPPORT_USBPLUG 184 /* 185 * For RK3576 USBPLUG, should clear maskrom flag both in os_reg0 and os_reg16. 186 * It already clear os_reg16 under ./drivers/usb/gadget/f_rockusb.c 187 */ 188 if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) != BOOT_BROM_DOWNLOAD) 189 writel(0, (void *)PMU1_GRF_BASE + OS_REG0); 190 #endif 191 } 192 193 void board_set_iomux(enum if_type if_type, int devnum, int routing) 194 { 195 switch (if_type) { 196 case IF_TYPE_MMC: 197 if (devnum == 0) { 198 writel(0xffff1111, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L); 199 writel(0xffff1111, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_H); 200 writel(0xffff1111, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L); 201 } else if (devnum == 1) { 202 writel(0xffff1111, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L); 203 writel(0x00ff0011, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H); 204 /* Pull up */ 205 writel(0x0FFF0FFF, VCCIO_IOC_BASE + VCCIO_IOC_GPIO2A_PUL); 206 } 207 break; 208 case IF_TYPE_MTD: 209 if (routing == 0) { 210 /* FSPI0 M0 */ 211 writel(0xffff2222, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L); 212 writel(0xffff2020, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L); 213 } else if (routing == 1) { 214 /* FSPI1 M0 */ 215 writel(0xffff2222, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L); 216 writel(0x00ff0022, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H); 217 /* Pull up */ 218 writel(0x03ff03ff, VCCIO_IOC_BASE + VCCIO_IOC_GPIO2A_PUL); 219 } else if (routing == 2) { 220 /* FSPI1 M1 */ 221 writel(0xf0003000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_L); 222 writel(0xffff3333, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_H); 223 writel(0x00f00030, TOP_IOC_BASE + GPIO1D_IOMUX_SEL_H); 224 /* Pull up */ 225 writel(0xffc0ffc0, VCCIO_IOC_BASE + VCCIO_IOC_GPIO1C_PUL); 226 } 227 break; 228 default: 229 printf("Bootdev 0x%x is not support\n", if_type); 230 } 231 } 232 233 void board_unset_iomux(enum if_type if_type, int devnum, int routing) 234 { 235 switch (if_type) { 236 case IF_TYPE_MTD: 237 if (routing == 0) { 238 /* FSPI0 M0 -> GPIO */ 239 writel(0xffff0000, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L); 240 writel(0xffff0000, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L); 241 } else if (routing == 1) { 242 /* FSPI1 M0 -> GPIO */ 243 writel(0xffff0000, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L); 244 writel(0x00ff0000, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H); 245 } else if (routing == 2) { 246 /* FSPI1 M1 -> GPIO */ 247 writel(0xf0000000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_L); 248 writel(0xffff0000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_H); 249 writel(0x00f00000, TOP_IOC_BASE + GPIO1D_IOMUX_SEL_H); 250 } 251 break; 252 default: 253 break; 254 } 255 } 256 257 /* @brief: release reset for MCU 258 * @param id: id of MCU, like: bus_mcu, pmu_mcu 259 * @param entry_point: entry of firmware, use for address map 260 * */ 261 int fit_standalone_release(char *id, uintptr_t entry_point) 262 { 263 if (!strcmp(id, "bus_mcu")) { 264 /* address map: map 0 to entry_point */ 265 sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID, 266 ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR, 267 entry_point); 268 269 /* 270 * bus m0 configuration: 271 * open bus m0 rtc / core / biu / root 272 */ 273 writel(0x5c000000, TOP_CRU_BASE + TOP_CRU_GATE_CON19); 274 275 /* select bus m0 jtag GPIO2A2 GPIO2A3 */ 276 //writel(0x003f0010, SYS_GRF_BASE + SYS_GRF_SOC_CON7); 277 //writel(0xff009900, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L); 278 279 /* release bus m0 jtag / core / biu */ 280 writel(0x38000000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON19); 281 } 282 else if (!strcmp(id, "pmu_mcu")) { 283 284 /* pmu m0 configuration: */ 285 /* open pmu m0 rtc / core / biu / root */ 286 /* writel(0x59020000, PMU1_CRU_BASE + PMU1_CRU_GATE_CON03); */ 287 288 /* select pmu m0 jtag */ 289 /* writel(0x003f0008, SYS_GRF_BASE + SYS_GRF_SOC_CON7); */ 290 /* writel(0xff009900, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L); */ 291 292 /* release pmu m0 jtag / core / biu */ 293 /* writel(0x38000000, PMU1_CRU_BASE + PMU1_CRU_SOFTRST_CON03); */ 294 } 295 296 return 0; 297 } 298 299 #ifndef CONFIG_TPL_BUILD 300 int arch_cpu_init(void) 301 { 302 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG) 303 u32 val; 304 305 /* Set the emmc to access ddr memory */ 306 val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2); 307 writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2); 308 309 /* Set the sdmmc0 to access ddr memory */ 310 val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5); 311 writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5); 312 313 /* Set the UFS to access ddr memory */ 314 val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3); 315 writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3); 316 317 /* Set the fspi0 and fspi1 to access ddr memory */ 318 val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4); 319 writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4); 320 321 /* Set the decom to access ddr memory */ 322 val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1); 323 writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1); 324 325 /* UFS PHY select 26M from ppll */ 326 writel(0x00030002, PMU1_CRU_BASE + PMU1_CRU_CLKSEL_CON03); 327 328 /* set iomux UFS_REFCLK, UFS_RSTN */ 329 writel(0x00FF0011, VCCIO7_IOC_BASE + VCCIO7_IOC_GPIO4D_IOMUX_SEL_L); 330 /* set UFS_RSTN to high */ 331 udelay(20); 332 writel(0x00100010, VCCIO7_IOC_BASE + VCCIO7_IOC_XIN_UFS_CON); 333 334 /* 335 * Set the GPIO0B0~B3 pull up and input enable. 336 * Keep consistent with other IO. 337 */ 338 writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L); 339 writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L); 340 341 /* 342 * bus mcu_cache_peripheral_addr 343 * The uncache area ranges from 0x20000000 to 0x48200000 344 * and contains rpmsg shared memory 345 */ 346 writel(0x20000000, SYS_SGRF_BASE + SYS_SGRF_SOC_CON14); 347 writel(0x48200000, SYS_SGRF_BASE + SYS_SGRF_SOC_CON15); 348 349 /* 350 * pmu mcu_cache_peripheral_addr 351 * The uncache area ranges from 0x20000000 to 0x48200000 352 * and contains rpmsg shared memory 353 */ 354 /* writel(0x20000000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON10); */ 355 /* writel(0x48200000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON11); */ 356 357 /* TODO: pmu mcu code addr need bl31 support */ 358 /* writel(0x48200000, 0x26002030); */ 359 360 /* 361 * Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0, 362 * keep consistent with other pwm. 363 */ 364 writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2); 365 366 /* 367 * Assert reset the combophy0 and combophy1, 368 * de-assert reset in Kernel combophy driver. 369 */ 370 writel(0x01200120, TOP_CRU_BASE + PHPPHYSOFTRST_CON01); 371 372 /* 373 * Assert SIDDQ for USB 2.0 PHY1 to power down 374 * PHY1 analog block to save power. And let the 375 * PHY0 for OTG0 interface still in normal mode. 376 */ 377 writel(0x20002000, USB2PHY1_GRF_BASE + USB2PHY_GRF_CON4); 378 379 /* 380 * Enable USB to DEBUG 381 * 1. Set linestate timeout 8ms 382 * 2. Set linestate fiter time 500us 383 * 3. Set Rx timeout counter for RX pulldown 2s 384 * 4. Set handshake counter number for SE0 and 385 * SE1 sequence at least 5. 386 */ 387 writel(0xff, USB2PHY0_GRF_BASE + USB2PHY_GRF_LS_TIMEOUT); 388 writel(0x10, USB2PHY0_GRF_BASE + USB2PHY_GRF_LS_DEB); 389 writel(0xffff, USB2PHY0_GRF_BASE + USB2PHY_GRF_RX_TIMEOUT); 390 writel(0x05, USB2PHY0_GRF_BASE + USB2PHY_GRF_SEQ_LIMT); 391 writel(0x00010001, USB2PHY0_GRF_BASE + USB2PHY_GRF_DBG_CON); 392 393 /* Enable noc slave response timeout */ 394 writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11); 395 writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12); 396 397 /* 398 * Select usb otg0 pipe phy status to 0 that 399 * ensure rockusb can work at high-speed even 400 * if usb3 phy isn't ready. 401 */ 402 writel(0x000c0008, USBGRF_BASE + USB_GRF_USB3OTG0_CON1); 403 404 /* 405 * Enable cci channels for below module AXI R/W 406 * Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3) 407 */ 408 writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20); 409 #endif 410 411 #if defined(CONFIG_ROCKCHIP_EMMC_IOMUX) 412 board_set_iomux(IF_TYPE_MMC, 0, 0); 413 #elif defined(CONFIG_ROCKCHIP_SFC_IOMUX) 414 /* 415 * (IF_TYPE_MTD, 0, 0) FSPI0 416 * (IF_TYPE_MTD, 1, 0) FSPI1 M0 417 * (IF_TYPE_MTD, 2, 0) FSPI1 M1 418 */ 419 board_set_iomux(IF_TYPE_MTD, 0, 0); 420 #endif /* #if defined(CONFIG_ROCKCHIP_EMMC_IOMUX) */ 421 422 return 0; 423 } 424 #endif 425 426 #if defined(CONFIG_SCSI) && defined(CONFIG_CMD_SCSI) && defined(CONFIG_UFS) 427 int rk_board_dm_fdt_fixup(const void *blob) 428 { 429 struct blk_desc *desc = rockchip_get_bootdev(); 430 const char *status = NULL; 431 int node = -1; 432 433 /* 434 * 1. Kernel DTS will enable UFS by default. 435 * 436 * 2. It hangs if Kernel UFS driver tries to access UFS registers when there 437 * is no power supply for UFS. 438 * 439 * So generally, disable UFS when detect fail. 440 * 441 * To save time spent on detecting UFS, you can disable UFS in kernel dts or 442 * U-Boot defconfig. 443 * 444 */ 445 if (desc->if_type != IF_TYPE_SCSI) { 446 node = fdt_path_offset(blob, "/ufs@2a2d0000"); 447 if (node >= 0) { 448 status = fdt_getprop(blob, node, "status", NULL); 449 if (status && strcmp(status, "disabled")) { 450 if (scsi_scan(true)) { 451 fdt_setprop((void *)blob, node, "status", "disabled", 9); 452 printf("FDT: UFS was not detected, disabling UFS.\n"); 453 } 454 } 455 } 456 } 457 458 node = fdt_path_offset(blob, "/sata@2a240000"); 459 if (node >= 0) { 460 /* 461 * Set SATA FBSCP and PORTS_IMPL for kernel drivers 462 */ 463 writel(SATA_FBS_ENABLE, SATA0_BASE_ADDR + SATA_PORT_CMD); 464 writel(1, SATA0_BASE_ADDR + SATA_PI); 465 writel(SATA_FBS_ENABLE, SATA1_BASE_ADDR + SATA_PORT_CMD); 466 writel(1, SATA1_BASE_ADDR + SATA_PI); 467 } 468 469 return 0; 470 } 471 #endif 472 473