1 /* 2 * Copyright (c) 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/arch/grf_rk3308.h> 9 #include <asm/arch/hardware.h> 10 #include <asm/gpio.h> 11 #include <debug_uart.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 #ifdef CONFIG_ARM64 16 #include <asm/armv8/mmu.h> 17 static struct mm_region rk3308_mem_map[] = { 18 { 19 .virt = 0x0UL, 20 .phys = 0x0UL, 21 .size = 0xff000000UL, 22 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 23 PTE_BLOCK_INNER_SHARE 24 }, { 25 .virt = 0xff000000UL, 26 .phys = 0xff000000UL, 27 .size = 0x01000000UL, 28 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 29 PTE_BLOCK_NON_SHARE | 30 PTE_BLOCK_PXN | PTE_BLOCK_UXN 31 }, { 32 /* List terminator */ 33 0, 34 } 35 }; 36 37 struct mm_region *mem_map = rk3308_mem_map; 38 #endif 39 40 #define GRF_BASE 0xff000000 41 #define SGRF_BASE 0xff2b0000 42 43 enum { 44 45 GPIO1C7_SHIFT = 8, 46 GPIO1C7_MASK = GENMASK(11, 8), 47 GPIO1C7_GPIO = 0, 48 GPIO1C7_UART1_RTSN, 49 GPIO1C7_UART2_TX_M0, 50 GPIO1C7_SPI2_MOSI, 51 GPIO1C7_JTAG_TMS, 52 53 GPIO1C6_SHIFT = 4, 54 GPIO1C6_MASK = GENMASK(7, 4), 55 GPIO1C6_GPIO = 0, 56 GPIO1C6_UART1_CTSN, 57 GPIO1C6_UART2_RX_M0, 58 GPIO1C6_SPI2_MISO, 59 GPIO1C6_JTAG_TCLK, 60 61 GPIO4D3_SHIFT = 6, 62 GPIO4D3_MASK = GENMASK(7, 6), 63 GPIO4D3_GPIO = 0, 64 GPIO4D3_SDMMC_D3, 65 GPIO4D3_UART2_TX_M1, 66 67 GPIO4D2_SHIFT = 4, 68 GPIO4D2_MASK = GENMASK(5, 4), 69 GPIO4D2_GPIO = 0, 70 GPIO4D2_SDMMC_D2, 71 GPIO4D2_UART2_RX_M1, 72 73 UART2_IO_SEL_SHIFT = 2, 74 UART2_IO_SEL_MASK = GENMASK(3, 2), 75 UART2_IO_SEL_M0 = 0, 76 UART2_IO_SEL_M1, 77 UART2_IO_SEL_USB, 78 }; 79 80 enum { 81 IOVSEL3_CTRL_SHIFT = 8, 82 IOVSEL3_CTRL_MASK = BIT(8), 83 VCCIO3_SEL_BY_GPIO = 0, 84 VCCIO3_SEL_BY_IOVSEL3, 85 86 IOVSEL3_SHIFT = 3, 87 IOVSEL3_MASK = BIT(3), 88 VCCIO3_3V3 = 0, 89 VCCIO3_1V8, 90 }; 91 92 /* 93 * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc 94 * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults 95 * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware, 96 * then we can switch to io_vsel3 after system power on, and release GPIO0_A4 97 * for other usage. 98 */ 99 100 #define GPIO0_A4 4 101 102 int rk_board_init(void) 103 { 104 static struct rk3308_grf * const grf = (void *)GRF_BASE; 105 u32 val; 106 int ret; 107 108 ret = gpio_request(GPIO0_A4, "gpio0_a4"); 109 if (ret < 0) { 110 printf("request for gpio0_a4 failed:%d\n", ret); 111 return 0; 112 } 113 114 gpio_direction_input(GPIO0_A4); 115 116 if (gpio_get_value(GPIO0_A4)) 117 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT | 118 VCCIO3_1V8 << IOVSEL3_SHIFT; 119 else 120 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT | 121 VCCIO3_3V3 << IOVSEL3_SHIFT; 122 rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val); 123 124 gpio_free(GPIO0_A4); 125 return 0; 126 } 127 128 void board_debug_uart_init(void) 129 { 130 static struct rk3308_grf * const grf = (void *)GRF_BASE; 131 132 if (gd && gd->serial.using_pre_serial) 133 return; 134 135 /* Enable early UART2 channel m1 on the rk3308 */ 136 rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK, 137 UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT); 138 rk_clrsetreg(&grf->gpio4d_iomux, 139 GPIO4D3_MASK | GPIO4D2_MASK, 140 GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT | 141 GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT); 142 } 143 144 #if defined(CONFIG_SPL_BUILD) 145 int arch_cpu_init(void) 146 { 147 static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE; 148 149 /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */ 150 rk_clrreg(&sgrf->con_secure0, 0x2b83); 151 152 return 0; 153 } 154 #endif 155