1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <ram.h> 9 #include <asm/io.h> 10 #include <asm/arch/rk_atags.h> 11 #include <asm/arch/param.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 #define SZ_4GB 0x100000000ULL 16 17 #ifndef CONFIG_SPL_BUILD 18 #define SDRAM_OFFSET(offset) (CONFIG_SYS_SDRAM_BASE + (offset)) 19 #define PARAM_DRAM_INFO_OFFSET (SZ_32M) 20 #define PARAM_OPTEE_INFO_OFFSET (SZ_32M + SZ_2M) 21 22 struct tos_param_t { 23 u32 version; 24 u32 checksum; 25 struct { 26 char name[8]; 27 s64 phy_addr; 28 u32 size; 29 u32 flags; 30 } tee_mem; 31 struct { 32 char name[8]; 33 s64 phy_addr; 34 u32 size; 35 u32 flags; 36 } drm_mem; 37 s64 reserve[8]; 38 }; 39 40 static uint16_t trust_checksum(const uint8_t *buf, uint16_t len) 41 { 42 uint16_t i, checksum = 0; 43 44 for (i = 0; i < len; i++) { 45 if (i % 2) 46 checksum += buf[i] << 8; 47 else 48 checksum += buf[i]; 49 } 50 checksum = ~checksum; 51 52 return checksum; 53 } 54 55 struct memblock param_parse_atf_mem(void) 56 { 57 struct memblock mem; 58 59 mem.base = 0; 60 mem.size = 0; 61 62 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 63 struct tag *t = NULL; 64 65 /* 66 * Get memory region of ATF 67 * 68 * 1. New way: atags info; 69 * 2. Leagcy way: 2MB size and start from ddr 0x0 offset; 70 */ 71 t = atags_get_tag(ATAG_ATF_MEM); 72 if (t && t->u.atf_mem.size) { 73 mem.base = t->u.atf_mem.phy_addr; 74 mem.size = t->u.atf_mem.size; 75 /* Sanity */ 76 if (mem.base + mem.size > SDRAM_OFFSET(SZ_1M)) { 77 printf("%s: ATF reserved region is not within 0-1MB " 78 "offset(0x%08llx-0x%08llx)!\n", 79 __func__, (u64)mem.base, (u64)mem.base + mem.size); 80 return mem; 81 } 82 } 83 #endif 84 85 /* Legacy */ 86 if (!mem.size) { 87 if (IS_ENABLED(CONFIG_ARM64) || 88 IS_ENABLED(CONFIG_ARM64_BOOT_AARCH32)) { 89 mem.base = SDRAM_OFFSET(0); 90 mem.size = SZ_1M; 91 } 92 } 93 94 debug("ATF: 0x%llx - 0x%llx\n", (u64)mem.base, (u64)mem.base + mem.size); 95 96 return mem; 97 } 98 99 struct memblock param_parse_optee_mem(void) 100 { 101 struct tos_param_t *tos_parameter; 102 struct memblock mem; 103 u32 checksum; 104 105 mem.base = 0; 106 mem.size = 0; 107 108 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 109 struct tag *t = NULL; 110 111 /* 112 * Get memory region of OP-TEE 113 * 114 * 1. New way: atags info; 115 * 2. Leagcy way: info in ddr 34M offset; 116 */ 117 t = atags_get_tag(ATAG_TOS_MEM); 118 if (t && (t->u.tos_mem.tee_mem.flags == 1)) { 119 mem.base = t->u.tos_mem.tee_mem.phy_addr; 120 mem.size = t->u.tos_mem.tee_mem.size; 121 } 122 #endif 123 124 /* Legacy */ 125 if (!mem.size) { 126 tos_parameter = 127 (struct tos_param_t *)(SDRAM_OFFSET(PARAM_OPTEE_INFO_OFFSET)); 128 checksum = 129 trust_checksum((uint8_t *)(unsigned long)tos_parameter + 8, 130 sizeof(struct tos_param_t) - 8); 131 if ((checksum == tos_parameter->checksum) && 132 (tos_parameter->tee_mem.flags == 1)) { 133 mem.base = tos_parameter->tee_mem.phy_addr; 134 mem.size = tos_parameter->tee_mem.size; 135 } 136 } 137 138 if (mem.size) 139 gd->flags |= GD_FLG_BL32_ENABLED; 140 141 debug("TOS: 0x%llx - 0x%llx\n", (u64)mem.base, (u64)mem.base + mem.size); 142 143 return mem; 144 } 145 146 struct memblock param_parse_common_resv_mem(void) 147 { 148 struct memblock mem; 149 150 #if defined(CONFIG_ARM64) 151 mem.base = SDRAM_OFFSET(SZ_1M); 152 mem.size = SZ_1M; 153 /* 154 * The ARMv8 platform enabling AArch32 mode should reserve memory the same 155 * as AArch64 mode(because there is no difference about ATF), only some 156 * platform has special request, they are: RK3308. 157 */ 158 #elif defined(CONFIG_ARM64_BOOT_AARCH32) && !defined(CONFIG_ROCKCHIP_RK3308) 159 mem.base = SDRAM_OFFSET(SZ_1M); 160 mem.size = SZ_1M; 161 #else 162 mem.size = 0; 163 #endif 164 return mem; 165 } 166 167 int param_parse_assign_bootdev(char **devtype, char **devnum) 168 { 169 char *bootdev_str = CONFIG_ROCKCHIP_BOOTDEV; 170 char *type, *num; 171 172 num = strchr(bootdev_str, ' '); 173 if (!num) 174 return -ENODEV; 175 176 type = strdup(bootdev_str); 177 type[num - bootdev_str] = 0; 178 num++; 179 180 *devtype = type; 181 *devnum = num; 182 183 return 0; 184 } 185 186 int param_parse_atags_bootdev(char **devtype, char **devnum) 187 { 188 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 189 struct tag *t; 190 191 t = atags_get_tag(ATAG_BOOTDEV); 192 if (t) { 193 switch (t->u.bootdev.devtype) { 194 #ifdef CONFIG_DM_MMC 195 case BOOT_TYPE_EMMC: 196 *devtype = "mmc"; 197 *devnum = "0"; 198 break; 199 case BOOT_TYPE_SD0: 200 case BOOT_TYPE_SD1: 201 *devtype = "mmc"; 202 *devnum = "1"; 203 /* 204 * If preloader does not pass sdupdate value, we treat it 205 * as a unknown card and call the rkimgtest cmd to find 206 * out what it is. 207 * 208 * If preloader pass sdupdate value as an update card, 209 * we just set "sdfwupdate" to bootargs instead of 210 * calling rkimgtest cmd which consumes time. 211 */ 212 if (t->u.bootdev.sdupdate == SD_UNKNOWN_CARD) { 213 run_command("mmc dev 1", 0); 214 run_command("rkimgtest mmc 1", 0); 215 } else if (t->u.bootdev.sdupdate == SD_UPDATE_CARD) { 216 env_update("bootargs", "sdfwupdate"); 217 } 218 break; 219 #endif 220 #if defined(CONFIG_RKNAND) || defined(CONFIG_RKNANDC_NAND) 221 case BOOT_TYPE_NAND: 222 *devtype = "rknand"; 223 *devnum = "0"; 224 break; 225 #endif 226 #ifdef CONFIG_RKSFC_NAND 227 case BOOT_TYPE_SPI_NAND: 228 *devtype = "spinand"; 229 *devnum = "0"; 230 break; 231 #endif 232 #ifdef CONFIG_RKSFC_NOR 233 case BOOT_TYPE_SPI_NOR: 234 *devtype = "spinor"; 235 *devnum = "1"; 236 break; 237 #endif 238 #ifdef CONFIG_DM_RAMDISK 239 case BOOT_TYPE_RAM: 240 *devtype = "ramdisk"; 241 *devnum = "0"; 242 break; 243 #endif 244 #ifdef CONFIG_NAND 245 case BOOT_TYPE_MTD_BLK_NAND: 246 *devtype = "mtd"; 247 *devnum = "0"; 248 break; 249 #endif 250 #ifdef CONFIG_MTD_SPI_NAND 251 case BOOT_TYPE_MTD_BLK_SPI_NAND: 252 *devtype = "mtd"; 253 *devnum = "1"; 254 break; 255 #endif 256 #ifdef CONFIG_SPI_FLASH_MTD 257 case BOOT_TYPE_MTD_BLK_SPI_NOR: 258 *devtype = "mtd"; 259 *devnum = "2"; 260 break; 261 #endif 262 default: 263 printf("Unknown bootdev type: 0x%x\n", 264 t->u.bootdev.devtype); 265 return -EINVAL; 266 } 267 268 return 0; 269 } 270 #endif 271 272 return -ENOSYS; 273 } 274 #endif 275 276 static phys_size_t ddr_mem_get_usable_size(u64 base, u64 size) 277 { 278 return (base + size >= CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE) ? 279 (CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE - base) : size; 280 } 281 282 struct memblock *param_parse_ddr_mem(int *out_count) 283 { 284 struct udevice *dev; 285 struct memblock *mem; 286 struct ram_info ram; 287 int i, ret, count; 288 289 /* 290 * Get memory region of DDR 291 * 292 * 1. New: atags info; 293 * 2. Leagcy: os register; 294 */ 295 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 296 struct tag *t; 297 u64 base, size; 298 int n; 299 300 t = atags_get_tag(ATAG_DDR_MEM); 301 if (t && t->u.ddr_mem.count) { 302 /* extend top ram size */ 303 if (t->u.ddr_mem.flags & DDR_MEM_FLG_EXT_TOP) 304 gd->ram_top_ext_size = t->u.ddr_mem.data[0]; 305 306 /* normal ram size */ 307 count = t->u.ddr_mem.count; 308 mem = calloc(count + MEM_RESV_COUNT, sizeof(*mem)); 309 if (!mem) { 310 printf("Calloc ddr memory failed\n"); 311 return 0; 312 } 313 314 for (i = 0, n = 0; i < count; i++, n++) { 315 base = t->u.ddr_mem.bank[i]; 316 size = t->u.ddr_mem.bank[i + count]; 317 318 /* 0~4GB */ 319 if (base < SZ_4GB) { 320 mem[n].base = base; 321 mem[n].size = ddr_mem_get_usable_size(base, size); 322 if (base + size > SZ_4GB) { 323 n++; 324 mem[n].base_u64 = SZ_4GB; 325 mem[n].size_u64 = base + size - SZ_4GB; 326 } 327 } else { 328 /* 4GB+ */ 329 mem[n].base_u64 = base; 330 mem[n].size_u64 = size; 331 } 332 333 assert(n < count + MEM_RESV_COUNT); 334 } 335 336 *out_count = n; 337 return mem; 338 } 339 #endif 340 341 /* Leagcy */ 342 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 343 if (ret) { 344 debug("DRAM init failed: %d\n", ret); 345 return NULL; 346 } 347 ret = ram_get_info(dev, &ram); 348 if (ret) { 349 debug("Cannot get DRAM size: %d\n", ret); 350 return NULL; 351 } 352 353 debug("SDRAM base=%lx, size=%lx\n", 354 (unsigned long)ram.base, (unsigned long)ram.size); 355 356 count = 1; 357 mem = calloc(1, sizeof(*mem)); 358 if (!mem) { 359 printf("Calloc ddr memory failed\n"); 360 return 0; 361 } 362 363 for (i = 0; i < count; i++) { 364 mem[i].base = CONFIG_SYS_SDRAM_BASE; 365 mem[i].size = ddr_mem_get_usable_size(mem[i].base, ram.size); 366 } 367 368 *out_count = count; 369 return mem; 370 } 371 372 #ifndef CONFIG_BIDRAM 373 /* 374 * init_bank=0: called from dram_init_banksize() 375 * init_bank=0: called from dram_init() 376 */ 377 phys_size_t param_simple_parse_ddr_mem(int init_bank) 378 { 379 struct memblock *list; 380 int i, count; 381 382 list = param_parse_ddr_mem(&count); 383 if (!list) { 384 printf("Can't get dram banks\n"); 385 return 0; 386 } 387 388 if (count > CONFIG_NR_DRAM_BANKS) { 389 printf("Dram banks num=%d, over %d\n", count, CONFIG_NR_DRAM_BANKS); 390 return 0; 391 } 392 393 if (!init_bank) { 394 i = count - 1; 395 return ddr_mem_get_usable_size(list[i].base, list[i].size); 396 } 397 398 for (i = 0; i < count; i++) { 399 gd->bd->bi_dram[i].start = list[i].base; 400 gd->bd->bi_dram[i].size = 401 ddr_mem_get_usable_size(list[i].base, list[i].size); 402 debug("bank[%d]: 0x%08lx - 0x%08lx\n", i, 403 (ulong)gd->bd->bi_dram[i].start, 404 (ulong)gd->bd->bi_dram[i].start + 405 (ulong)gd->bd->bi_dram[i].size); 406 } 407 408 return 0; 409 } 410 #endif 411 412 int param_parse_pre_serial(int *flags) 413 { 414 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 415 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 416 struct tag *t; 417 418 t = atags_get_tag(ATAG_SERIAL); 419 if (t) { 420 gd->serial.using_pre_serial = 1; 421 gd->serial.enable = t->u.serial.enable; 422 gd->serial.baudrate = t->u.serial.baudrate; 423 gd->serial.addr = t->u.serial.addr; 424 gd->serial.id = t->u.serial.id; 425 gd->baudrate = CONFIG_BAUDRATE; 426 if (!gd->serial.enable && flags) 427 *flags |= GD_FLG_DISABLE_CONSOLE; 428 debug("preloader: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 429 gd->serial.enable, gd->serial.addr, 430 gd->serial.baudrate, gd->serial.id); 431 } else 432 #endif 433 { 434 gd->baudrate = CONFIG_BAUDRATE; 435 gd->serial.baudrate = CONFIG_BAUDRATE; 436 gd->serial.addr = CONFIG_DEBUG_UART_BASE; 437 } 438 439 return 0; 440 } 441 442 int param_parse_pubkey_fuse_programmed(void) 443 { 444 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 445 struct tag *t; 446 447 t = atags_get_tag(ATAG_PUB_KEY); 448 if (t) { 449 /* Pass if efuse/otp programmed */ 450 if (t->u.pub_key.flag == PUBKEY_FUSE_PROGRAMMED) 451 env_update("bootargs", "fuse.programmed=1"); 452 else 453 env_update("bootargs", "fuse.programmed=0"); 454 } 455 #endif 456 return 0; 457 } 458 459