1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <amp.h> 9 #include <bidram.h> 10 #include <boot_rkimg.h> 11 #include <cli.h> 12 #include <clk.h> 13 #include <console.h> 14 #include <debug_uart.h> 15 #include <dm.h> 16 #include <dvfs.h> 17 #include <io-domain.h> 18 #include <key.h> 19 #include <memblk.h> 20 #include <misc.h> 21 #include <of_live.h> 22 #include <ram.h> 23 #include <rockchip_debugger.h> 24 #include <syscon.h> 25 #include <sysmem.h> 26 #include <video_rockchip.h> 27 #include <asm/io.h> 28 #include <asm/gpio.h> 29 #include <dm/uclass-internal.h> 30 #include <dm/root.h> 31 #include <power/charge_display.h> 32 #include <power/regulator.h> 33 #include <asm/arch/boot_mode.h> 34 #include <asm/arch/clock.h> 35 #include <asm/arch/cpu.h> 36 #include <asm/arch/hotkey.h> 37 #include <asm/arch/param.h> 38 #include <asm/arch/periph.h> 39 #include <asm/arch/resource_img.h> 40 #include <asm/arch/rk_atags.h> 41 #include <asm/arch/vendor.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 __weak int rk_board_late_init(void) 46 { 47 return 0; 48 } 49 50 __weak int rk_board_fdt_fixup(void *blob) 51 { 52 return 0; 53 } 54 55 __weak int soc_clk_dump(void) 56 { 57 return 0; 58 } 59 60 __weak int set_armclk_rate(void) 61 { 62 return 0; 63 } 64 65 __weak int rk_board_init(void) 66 { 67 return 0; 68 } 69 70 /* 71 * define serialno max length, the max length is 512 Bytes 72 * The remaining bytes are used to ensure that the first 512 bytes 73 * are valid when executing 'env_set("serial#", value)'. 74 */ 75 #define VENDOR_SN_MAX 513 76 #define CPUID_LEN 0x10 77 #define CPUID_OFF 0x07 78 79 static int rockchip_set_ethaddr(void) 80 { 81 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 82 char buf[ARP_HLEN_ASCII + 1]; 83 u8 ethaddr[ARP_HLEN]; 84 int ret; 85 86 ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr)); 87 if (ret > 0 && is_valid_ethaddr(ethaddr)) { 88 sprintf(buf, "%pM", ethaddr); 89 env_set("ethaddr", buf); 90 } 91 #endif 92 return 0; 93 } 94 95 static int rockchip_set_serialno(void) 96 { 97 u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2]; 98 u8 cpuid[CPUID_LEN] = {0}; 99 char serialno_str[VENDOR_SN_MAX]; 100 int ret = 0, i; 101 u64 serialno; 102 103 /* Read serial number from vendor storage part */ 104 memset(serialno_str, 0, VENDOR_SN_MAX); 105 106 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 107 ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1)); 108 if (ret > 0) { 109 env_set("serial#", serialno_str); 110 } else { 111 #endif 112 #ifdef CONFIG_ROCKCHIP_EFUSE 113 struct udevice *dev; 114 115 /* retrieve the device */ 116 ret = uclass_get_device_by_driver(UCLASS_MISC, 117 DM_GET_DRIVER(rockchip_efuse), 118 &dev); 119 if (ret) { 120 printf("%s: could not find efuse device\n", __func__); 121 return ret; 122 } 123 124 /* read the cpu_id range from the efuses */ 125 ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid)); 126 if (ret) { 127 printf("%s: read cpuid from efuses failed, ret=%d\n", 128 __func__, ret); 129 return ret; 130 } 131 #else 132 /* generate random cpuid */ 133 for (i = 0; i < CPUID_LEN; i++) 134 cpuid[i] = (u8)(rand()); 135 #endif 136 /* Generate the serial number based on CPU ID */ 137 for (i = 0; i < 8; i++) { 138 low[i] = cpuid[1 + (i << 1)]; 139 high[i] = cpuid[i << 1]; 140 } 141 142 serialno = crc32_no_comp(0, low, 8); 143 serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; 144 snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); 145 146 env_set("serial#", serialno_str); 147 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 148 } 149 #endif 150 151 return ret; 152 } 153 154 #if defined(CONFIG_USB_FUNCTION_FASTBOOT) 155 int fb_set_reboot_flag(void) 156 { 157 printf("Setting reboot to fastboot flag ...\n"); 158 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); 159 160 return 0; 161 } 162 #endif 163 164 #ifdef CONFIG_ROCKCHIP_USB_BOOT 165 static int boot_from_udisk(void) 166 { 167 struct blk_desc *desc; 168 char *devtype; 169 char *devnum; 170 171 devtype = env_get("devtype"); 172 devnum = env_get("devnum"); 173 174 /* Booting priority: mmc1 > udisk */ 175 if (!strcmp(devtype, "mmc") && !strcmp(devnum, "1")) 176 return 0; 177 178 if (!run_command("usb start", -1)) { 179 desc = blk_get_devnum_by_type(IF_TYPE_USB, 0); 180 if (!desc) { 181 printf("No usb device found\n"); 182 return -ENODEV; 183 } 184 185 if (!run_command("rkimgtest usb 0", -1)) { 186 rockchip_set_bootdev(desc); 187 env_set("devtype", "usb"); 188 env_set("devnum", "0"); 189 printf("Boot from usb 0\n"); 190 } else { 191 printf("No usb dev 0 found\n"); 192 return -ENODEV; 193 } 194 } 195 196 return 0; 197 } 198 #endif 199 200 static void cmdline_handle(void) 201 { 202 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 203 struct tag *t; 204 205 t = atags_get_tag(ATAG_PUB_KEY); 206 if (t) { 207 /* Pass if efuse/otp programmed */ 208 if (t->u.pub_key.flag == PUBKEY_FUSE_PROGRAMMED) 209 env_update("bootargs", "fuse.programmed=1"); 210 else 211 env_update("bootargs", "fuse.programmed=0"); 212 } 213 #endif 214 } 215 216 int board_late_init(void) 217 { 218 rockchip_set_ethaddr(); 219 rockchip_set_serialno(); 220 setup_download_mode(); 221 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 222 setup_boot_mode(); 223 #endif 224 #ifdef CONFIG_ROCKCHIP_USB_BOOT 225 boot_from_udisk(); 226 #endif 227 #ifdef CONFIG_DM_CHARGE_DISPLAY 228 charge_display(); 229 #endif 230 #ifdef CONFIG_DRM_ROCKCHIP 231 rockchip_show_logo(); 232 #endif 233 soc_clk_dump(); 234 cmdline_handle(); 235 236 return rk_board_late_init(); 237 } 238 239 #ifdef CONFIG_USING_KERNEL_DTB 240 /* Here, only fixup cru phandle, pmucru is not included */ 241 static int phandles_fixup_cru(void *fdt) 242 { 243 const char *props[] = { "clocks", "assigned-clocks" }; 244 struct udevice *dev; 245 struct uclass *uc; 246 const char *comp; 247 u32 id, nclocks; 248 u32 *clocks; 249 int phandle, ncells; 250 int off, offset; 251 int ret, length; 252 int i, j; 253 int first_phandle = -1; 254 255 phandle = -ENODATA; 256 ncells = -ENODATA; 257 258 /* fdt points to kernel dtb, getting cru phandle and "#clock-cells" */ 259 for (offset = fdt_next_node(fdt, 0, NULL); 260 offset >= 0; 261 offset = fdt_next_node(fdt, offset, NULL)) { 262 comp = fdt_getprop(fdt, offset, "compatible", NULL); 263 if (!comp) 264 continue; 265 266 /* Actually, this is not a good method to get cru node */ 267 off = strlen(comp) - strlen("-cru"); 268 if (off > 0 && !strncmp(comp + off, "-cru", 4)) { 269 phandle = fdt_get_phandle(fdt, offset); 270 ncells = fdtdec_get_int(fdt, offset, 271 "#clock-cells", -ENODATA); 272 break; 273 } 274 } 275 276 if (phandle == -ENODATA || ncells == -ENODATA) 277 return 0; 278 279 debug("%s: target cru: clock-cells:%d, phandle:0x%x\n", 280 __func__, ncells, fdt32_to_cpu(phandle)); 281 282 /* Try to fixup all cru phandle from U-Boot dtb nodes */ 283 for (id = 0; id < UCLASS_COUNT; id++) { 284 ret = uclass_get(id, &uc); 285 if (ret) 286 continue; 287 288 if (list_empty(&uc->dev_head)) 289 continue; 290 291 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 292 /* Only U-Boot node go further */ 293 if (!dev_read_bool(dev, "u-boot,dm-pre-reloc") && 294 !dev_read_bool(dev, "u-boot,dm-spl")) 295 continue; 296 297 for (i = 0; i < ARRAY_SIZE(props); i++) { 298 if (!dev_read_prop(dev, props[i], &length)) 299 continue; 300 301 clocks = malloc(length); 302 if (!clocks) 303 return -ENOMEM; 304 305 /* Read "props[]" which contains cru phandle */ 306 nclocks = length / sizeof(u32); 307 if (dev_read_u32_array(dev, props[i], 308 clocks, nclocks)) { 309 free(clocks); 310 continue; 311 } 312 313 /* Fixup with kernel cru phandle */ 314 for (j = 0; j < nclocks; j += (ncells + 1)) { 315 /* 316 * Check: update pmucru phandle with cru 317 * phandle by mistake. 318 */ 319 if (first_phandle == -1) 320 first_phandle = clocks[j]; 321 322 if (clocks[j] != first_phandle) { 323 debug("WARN: %s: first cru phandle=%d, this=%d\n", 324 dev_read_name(dev), 325 first_phandle, clocks[j]); 326 continue; 327 } 328 329 clocks[j] = phandle; 330 } 331 332 /* 333 * Override live dt nodes but not fdt nodes, 334 * because all U-Boot nodes has been imported 335 * to live dt nodes, should use "dev_xxx()". 336 */ 337 dev_write_u32_array(dev, props[i], 338 clocks, nclocks); 339 free(clocks); 340 } 341 } 342 } 343 344 return 0; 345 } 346 347 static int phandles_fixup_gpio(void *fdt, void *ufdt) 348 { 349 struct udevice *dev; 350 struct uclass *uc; 351 const char *prop = "gpios"; 352 const char *comp; 353 char *gpio_name[10]; 354 int gpio_off[10]; 355 int pinctrl; 356 int offset; 357 int i = 0; 358 int n = 0; 359 360 pinctrl = fdt_path_offset(fdt, "/pinctrl"); 361 if (pinctrl < 0) 362 return 0; 363 364 memset(gpio_name, 0, sizeof(gpio_name)); 365 for (offset = fdt_first_subnode(fdt, pinctrl); 366 offset >= 0; 367 offset = fdt_next_subnode(fdt, offset)) { 368 /* assume the font nodes are gpio node */ 369 if (++i >= ARRAY_SIZE(gpio_name)) 370 break; 371 372 comp = fdt_getprop(fdt, offset, "compatible", NULL); 373 if (!comp) 374 continue; 375 376 if (!strcmp(comp, "rockchip,gpio-bank")) { 377 gpio_name[n] = (char *)fdt_get_name(fdt, offset, NULL); 378 gpio_off[n] = offset; 379 n++; 380 } 381 } 382 383 if (!gpio_name[0]) 384 return 0; 385 386 if (uclass_get(UCLASS_KEY, &uc) || list_empty(&uc->dev_head)) 387 return 0; 388 389 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 390 u32 new_phd, phd_old; 391 char *name; 392 ofnode ofn; 393 394 if (!dev_read_bool(dev, "u-boot,dm-pre-reloc") && 395 !dev_read_bool(dev, "u-boot,dm-spl")) 396 continue; 397 398 if (dev_read_u32_array(dev, prop, &phd_old, 1)) 399 continue; 400 401 ofn = ofnode_get_by_phandle(phd_old); 402 if (!ofnode_valid(ofn)) 403 continue; 404 405 name = (char *)ofnode_get_name(ofn); 406 if (!name) 407 continue; 408 409 for (i = 0; i < ARRAY_SIZE(gpio_name[i]); i++) { 410 if (gpio_name[i] && !strcmp(name, gpio_name[i])) { 411 new_phd = fdt_get_phandle(fdt, gpio_off[i]); 412 dev_write_u32_array(dev, prop, &new_phd, 1); 413 break; 414 } 415 } 416 } 417 418 return 0; 419 } 420 421 __weak int board_mmc_dm_reinit(struct udevice *dev) 422 { 423 return 0; 424 } 425 426 static int mmc_dm_reinit(void) 427 { 428 struct udevice *dev; 429 struct uclass *uc; 430 int ret; 431 432 if (uclass_get(UCLASS_MMC, &uc) || list_empty(&uc->dev_head)) 433 return 0; 434 435 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 436 ret = board_mmc_dm_reinit(dev); 437 if (ret) 438 return ret; 439 } 440 441 return 0; 442 } 443 444 int init_kernel_dtb(void) 445 { 446 ulong fdt_addr; 447 void *ufdt_blob; 448 int ret; 449 450 fdt_addr = env_get_ulong("fdt_addr_r", 16, 0); 451 if (!fdt_addr) { 452 printf("No Found FDT Load Address.\n"); 453 return -1; 454 } 455 456 ret = rockchip_read_dtb_file((void *)fdt_addr); 457 if (ret < 0) { 458 if (!fdt_check_header(gd->fdt_blob_kern)) { 459 fdt_addr = (ulong)memalign(ARCH_DMA_MINALIGN, 460 fdt_totalsize(gd->fdt_blob_kern)); 461 if (!fdt_addr) 462 return -ENOMEM; 463 464 memcpy((void *)fdt_addr, gd->fdt_blob_kern, 465 fdt_totalsize(gd->fdt_blob_kern)); 466 printf("DTB: embedded kern.dtb\n"); 467 } else { 468 printf("Failed to get kernel dtb, ret=%d\n", ret); 469 return ret; 470 } 471 } 472 473 ufdt_blob = (void *)gd->fdt_blob; 474 gd->fdt_blob = (void *)fdt_addr; 475 476 hotkey_run(HK_FDT); 477 478 /* 479 * There is a phandle miss match between U-Boot and kernel dtb node, 480 * we fixup it in U-Boot live dt nodes. 481 * 482 * CRU: all nodes. 483 * GPIO: key nodes. 484 */ 485 phandles_fixup_cru((void *)gd->fdt_blob); 486 phandles_fixup_gpio((void *)gd->fdt_blob, (void *)ufdt_blob); 487 488 of_live_build((void *)gd->fdt_blob, (struct device_node **)&gd->of_root); 489 dm_scan_fdt((void *)gd->fdt_blob, false); 490 491 /* 492 * There maybe something for the mmc devices to do after kernel dtb 493 * dm setup, eg: regain the clock device binding from kernel dtb. 494 */ 495 mmc_dm_reinit(); 496 497 /* Reserve 'reserved-memory' */ 498 ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob); 499 if (ret) 500 return ret; 501 502 return 0; 503 } 504 #endif 505 506 void board_env_fixup(void) 507 { 508 struct memblock mem; 509 ulong u_addr_r; 510 phys_size_t end; 511 char *addr_r; 512 513 #ifdef ENV_MEM_LAYOUT_SETTINGS1 514 const char *env_addr0[] = { 515 "scriptaddr", "pxefile_addr_r", 516 "fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r", 517 }; 518 const char *env_addr1[] = { 519 "scriptaddr1", "pxefile_addr1_r", 520 "fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r", 521 }; 522 int i; 523 524 /* 128M is a typical ram size for most platform, so as default here */ 525 if (gd->ram_size <= SZ_128M) { 526 /* Replace orignal xxx_addr_r */ 527 for (i = 0; i < ARRAY_SIZE(env_addr1); i++) { 528 addr_r = env_get(env_addr1[i]); 529 if (addr_r) 530 env_set(env_addr0[i], addr_r); 531 } 532 } 533 #endif 534 /* If bl32 is disabled, maybe kernel can be load to lower address. */ 535 if (!(gd->flags & GD_FLG_BL32_ENABLED)) { 536 addr_r = env_get("kernel_addr_no_bl32_r"); 537 if (addr_r) 538 env_set("kernel_addr_r", addr_r); 539 /* If bl32 is enlarged, we move ramdisk addr right behind it */ 540 } else { 541 mem = param_parse_optee_mem(); 542 end = mem.base + mem.size; 543 u_addr_r = env_get_ulong("ramdisk_addr_r", 16, 0); 544 if (u_addr_r >= mem.base && u_addr_r < end) 545 env_set_hex("ramdisk_addr_r", end); 546 } 547 } 548 549 static void early_download(void) 550 { 551 #if defined(CONFIG_PWRKEY_DNL_TRIGGER_NUM) && \ 552 (CONFIG_PWRKEY_DNL_TRIGGER_NUM > 0) 553 if (pwrkey_download_init()) 554 printf("Pwrkey download init failed\n"); 555 #endif 556 557 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 558 if (is_hotkey(HK_BROM_DNL)) { 559 printf("Enter bootrom download..."); 560 flushc(); 561 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 562 do_reset(NULL, 0, 0, NULL); 563 printf("failed!\n"); 564 } 565 #endif 566 } 567 568 static void board_debug_init(void) 569 { 570 if (!gd->serial.using_pre_serial) 571 board_debug_uart_init(); 572 573 if (tstc()) { 574 gd->console_evt = getc(); 575 if (gd->console_evt <= 0x1a) /* 'z' */ 576 printf("Hotkey: ctrl+%c\n", gd->console_evt + 'a' - 1); 577 } 578 } 579 580 int board_init(void) 581 { 582 board_debug_init(); 583 584 #ifdef DEBUG 585 soc_clk_dump(); 586 #endif 587 588 #ifdef CONFIG_USING_KERNEL_DTB 589 init_kernel_dtb(); 590 #endif 591 early_download(); 592 593 /* 594 * pmucru isn't referenced on some platforms, so pmucru driver can't 595 * probe that the "assigned-clocks" is unused. 596 */ 597 clks_probe(); 598 #ifdef CONFIG_DM_REGULATOR 599 if (regulators_enable_boot_on(is_hotkey(HK_REGULATOR))) 600 debug("%s: Can't enable boot on regulator\n", __func__); 601 #endif 602 603 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 604 io_domain_init(); 605 #endif 606 607 set_armclk_rate(); 608 609 #ifdef CONFIG_DM_DVFS 610 dvfs_init(true); 611 #endif 612 613 return rk_board_init(); 614 } 615 616 int interrupt_debugger_init(void) 617 { 618 #ifdef CONFIG_ROCKCHIP_DEBUGGER 619 return rockchip_debugger_init(); 620 #else 621 return 0; 622 #endif 623 } 624 625 int board_fdt_fixup(void *blob) 626 { 627 /* Common fixup for DRM */ 628 #ifdef CONFIG_DRM_ROCKCHIP 629 rockchip_display_fixup(blob); 630 #endif 631 632 return rk_board_fdt_fixup(blob); 633 } 634 635 #ifdef CONFIG_ARM64_BOOT_AARCH32 636 /* 637 * Fixup MMU region attr for OP-TEE on ARMv8 CPU: 638 * 639 * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode. 640 * 641 * Command for OP-TEE: 642 * 64-bit mode: dcache is always enabled; 643 * 32-bit mode: dcache is always disabled(Due to some unknown issue); 644 * 645 * Command for U-Boot: 646 * 64-bit mode: MMU table is static defined in rkxxx.c file, all memory 647 * regions are mapped. That's good to match OP-TEE MMU policy. 648 * 649 * 32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where 650 * the OP-TEE region has been reserved, so it can not be 651 * mapped(i.e. dcache is disabled). That's also good to match 652 * OP-TEE MMU policy. 653 * 654 * For the data coherence when communication between U-Boot and OP-TEE, U-Boot 655 * should follow OP-TEE MMU policy. 656 * 657 * Here is the special: 658 * When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while 659 * OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE 660 * region(but OP-TEE requires it cacheable) so we fixup here. 661 */ 662 int board_initr_caches_fixup(void) 663 { 664 struct memblock mem; 665 666 mem = param_parse_optee_mem(); 667 if (mem.size) 668 mmu_set_region_dcache_behaviour(mem.base, mem.size, 669 DCACHE_WRITEBACK); 670 return 0; 671 } 672 #endif 673 674 void arch_preboot_os(uint32_t bootm_state) 675 { 676 if (bootm_state & BOOTM_STATE_OS_PREP) 677 hotkey_run(HK_CLI_OS_PRE); 678 } 679 680 void board_quiesce_devices(void) 681 { 682 hotkey_run(HK_CMDLINE); 683 hotkey_run(HK_CLI_OS_GO); 684 685 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 686 /* Destroy atags makes next warm boot safer */ 687 atags_destroy(); 688 #endif 689 690 #if defined(CONFIG_CONSOLE_RECORD) 691 /* Print record console data */ 692 console_record_print_purge(); 693 #endif 694 } 695 696 void enable_caches(void) 697 { 698 icache_enable(); 699 dcache_enable(); 700 } 701 702 #ifdef CONFIG_LMB 703 /* 704 * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". 705 * This makes lmb_alloc_base() always alloc from tail of sdram. 706 * If we don't assign it, bi_dram[0] is used by default and it may cause 707 * lmb_alloc_base() fail when bi_dram[0] range is small. 708 */ 709 void board_lmb_reserve(struct lmb *lmb) 710 { 711 char bootm_mapsize[32]; 712 char bootm_low[32]; 713 u64 start, size; 714 int i; 715 716 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 717 if (!gd->bd->bi_dram[i].size) 718 break; 719 } 720 721 start = gd->bd->bi_dram[i - 1].start; 722 size = gd->bd->bi_dram[i - 1].size; 723 724 /* 725 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+), 726 * otherwise "Unable to handle kernel paging request at virtual address ...". 727 * 728 * So that we hope limit highest address at 768M, but there comes the the 729 * problem: ramdisk is a compressed image and it expands after descompress, 730 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...". 731 * 732 * We make a appointment that the highest memory address is 512MB, it 733 * makes lmb alloc safer. 734 */ 735 #ifndef CONFIG_ARM64 736 if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) { 737 start = gd->bd->bi_dram[i - 2].start; 738 size = gd->bd->bi_dram[i - 2].size; 739 } 740 741 if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) 742 size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start; 743 #endif 744 sprintf(bootm_low, "0x%llx", start); 745 sprintf(bootm_mapsize, "0x%llx", size); 746 env_set("bootm_low", bootm_low); 747 env_set("bootm_mapsize", bootm_mapsize); 748 } 749 #endif 750 751 #ifdef CONFIG_BIDRAM 752 int board_bidram_reserve(struct bidram *bidram) 753 { 754 struct memblock mem; 755 int ret; 756 757 /* ATF */ 758 mem = param_parse_atf_mem(); 759 ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size); 760 if (ret) 761 return ret; 762 763 /* PSTORE/ATAGS/SHM */ 764 mem = param_parse_common_resv_mem(); 765 ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size); 766 if (ret) 767 return ret; 768 769 /* OP-TEE */ 770 mem = param_parse_optee_mem(); 771 ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size); 772 if (ret) 773 return ret; 774 775 return 0; 776 } 777 778 parse_fn_t board_bidram_parse_fn(void) 779 { 780 return param_parse_ddr_mem; 781 } 782 #endif 783 784 #ifdef CONFIG_ROCKCHIP_AMP 785 void cpu_secondary_init_r(void) 786 { 787 amp_cpus_on(); 788 } 789 #endif 790 791 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 792 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 793 int board_init_f_init_serial(void) 794 { 795 struct tag *t = atags_get_tag(ATAG_SERIAL); 796 797 if (t) { 798 gd->serial.using_pre_serial = t->u.serial.enable; 799 gd->serial.addr = t->u.serial.addr; 800 gd->serial.baudrate = t->u.serial.baudrate; 801 gd->serial.id = t->u.serial.id; 802 803 debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 804 __func__, gd->serial.using_pre_serial, 805 gd->serial.addr, gd->serial.baudrate, 806 gd->serial.id); 807 } 808 809 return 0; 810 } 811 #endif 812 813 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 814 #include <fdt_support.h> 815 #include <usb.h> 816 #include <usb/dwc2_udc.h> 817 818 static struct dwc2_plat_otg_data otg_data = { 819 .rx_fifo_sz = 512, 820 .np_tx_fifo_sz = 16, 821 .tx_fifo_sz = 128, 822 }; 823 824 int board_usb_init(int index, enum usb_init_type init) 825 { 826 const void *blob = gd->fdt_blob; 827 const fdt32_t *reg; 828 fdt_addr_t addr; 829 int node; 830 831 /* find the usb_otg node */ 832 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 833 834 retry: 835 if (node > 0) { 836 reg = fdt_getprop(blob, node, "reg", NULL); 837 if (!reg) 838 return -EINVAL; 839 840 addr = fdt_translate_address(blob, node, reg); 841 if (addr == OF_BAD_ADDR) { 842 pr_err("Not found usb_otg address\n"); 843 return -EINVAL; 844 } 845 846 #if defined(CONFIG_ROCKCHIP_RK3288) 847 if (addr != 0xff580000) { 848 node = fdt_node_offset_by_compatible(blob, node, 849 "snps,dwc2"); 850 goto retry; 851 } 852 #endif 853 } else { 854 /* 855 * With kernel dtb support, rk3288 dwc2 otg node 856 * use the rockchip legacy dwc2 driver "dwc_otg_310" 857 * with the compatible "rockchip,rk3288_usb20_otg", 858 * and rk3368 also use the "dwc_otg_310" driver with 859 * the compatible "rockchip,rk3368-usb". 860 */ 861 #if defined(CONFIG_ROCKCHIP_RK3288) 862 node = fdt_node_offset_by_compatible(blob, -1, 863 "rockchip,rk3288_usb20_otg"); 864 #elif defined(CONFIG_ROCKCHIP_RK3368) 865 node = fdt_node_offset_by_compatible(blob, -1, 866 "rockchip,rk3368-usb"); 867 #endif 868 if (node > 0) { 869 goto retry; 870 } else { 871 pr_err("Not found usb_otg device\n"); 872 return -ENODEV; 873 } 874 } 875 876 otg_data.regs_otg = (uintptr_t)addr; 877 878 return dwc2_udc_probe(&otg_data); 879 } 880 881 int board_usb_cleanup(int index, enum usb_init_type init) 882 { 883 return 0; 884 } 885 #endif 886