xref: /rk3399_rockchip-uboot/arch/arm/mach-rockchip/board.c (revision efda1f1db3f4fc77c65c060b5bdb91d223df5d69) 
1 /*
2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 #include <common.h>
7 #include <amp.h>
8 #include <clk.h>
9 #include <bidram.h>
10 #include <dm.h>
11 #include <debug_uart.h>
12 #include <memblk.h>
13 #include <ram.h>
14 #include <syscon.h>
15 #include <sysmem.h>
16 #include <asm/io.h>
17 #include <asm/arch/vendor.h>
18 #include <misc.h>
19 #include <asm/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/periph.h>
22 #include <asm/arch/boot_mode.h>
23 #include <asm/arch/rk_atags.h>
24 #include <asm/arch/param.h>
25 #ifdef CONFIG_DM_CHARGE_DISPLAY
26 #include <power/charge_display.h>
27 #endif
28 #ifdef CONFIG_DM_DVFS
29 #include <dvfs.h>
30 #endif
31 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
32 #include <io-domain.h>
33 #endif
34 #ifdef CONFIG_DM_REGULATOR
35 #include <power/regulator.h>
36 #endif
37 #ifdef CONFIG_DRM_ROCKCHIP
38 #include <video_rockchip.h>
39 #endif
40 #ifdef CONFIG_ROCKCHIP_DEBUGGER
41 #include <rockchip_debugger.h>
42 #endif
43 #include <of_live.h>
44 #include <dm/root.h>
45 #include <console.h>
46 
47 DECLARE_GLOBAL_DATA_PTR;
48 /* define serialno max length, the max length is 512 Bytes
49  * The remaining bytes are used to ensure that the first 512 bytes
50  * are valid when executing 'env_set("serial#", value)'.
51  */
52 #define VENDOR_SN_MAX	513
53 #define CPUID_LEN       0x10
54 #define CPUID_OFF       0x7
55 
56 static int rockchip_set_ethaddr(void)
57 {
58 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
59 	int ret;
60 	u8 ethaddr[ARP_HLEN];
61 	char buf[ARP_HLEN_ASCII + 1];
62 
63 	ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr));
64 	if (ret > 0 && is_valid_ethaddr(ethaddr)) {
65 		sprintf(buf, "%pM", ethaddr);
66 		env_set("ethaddr", buf);
67 	}
68 #endif
69 	return 0;
70 }
71 
72 static int rockchip_set_serialno(void)
73 {
74 	char serialno_str[VENDOR_SN_MAX];
75 	int ret = 0, i;
76 	u8 cpuid[CPUID_LEN] = {0};
77 	u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2];
78 	u64 serialno;
79 
80 	/* Read serial number from vendor storage part */
81 	memset(serialno_str, 0, VENDOR_SN_MAX);
82 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
83 	ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1));
84 	if (ret > 0) {
85 		env_set("serial#", serialno_str);
86 	} else {
87 #endif
88 #ifdef CONFIG_ROCKCHIP_EFUSE
89 		struct udevice *dev;
90 
91 		/* retrieve the device */
92 		ret = uclass_get_device_by_driver(UCLASS_MISC,
93 						  DM_GET_DRIVER(rockchip_efuse), &dev);
94 		if (ret) {
95 			printf("%s: could not find efuse device\n", __func__);
96 			return ret;
97 		}
98 		/* read the cpu_id range from the efuses */
99 		ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid));
100 		if (ret) {
101 			printf("%s: reading cpuid from the efuses failed\n", __func__);
102 			return ret;
103 		}
104 #else
105 		/* generate random cpuid */
106 		for (i = 0; i < CPUID_LEN; i++) {
107 			cpuid[i] = (u8)(rand());
108 		}
109 #endif
110 		/* Generate the serial number based on CPU ID */
111 		for (i = 0; i < 8; i++) {
112 			low[i] = cpuid[1 + (i << 1)];
113 			high[i] = cpuid[i << 1];
114 		}
115 		serialno = crc32_no_comp(0, low, 8);
116 		serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
117 		snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno);
118 
119 		env_set("serial#", serialno_str);
120 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
121 	}
122 #endif
123 	return ret;
124 }
125 
126 #if defined(CONFIG_USB_FUNCTION_FASTBOOT)
127 int fb_set_reboot_flag(void)
128 {
129 	printf("Setting reboot to fastboot flag ...\n");
130 	/* Set boot mode to fastboot */
131 	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
132 
133 	return 0;
134 }
135 #endif
136 
137 __weak int rk_board_init(void)
138 {
139 	return 0;
140 }
141 
142 __weak int rk_board_late_init(void)
143 {
144 	return 0;
145 }
146 
147 __weak int soc_clk_dump(void)
148 {
149 	return 0;
150 }
151 
152 __weak int set_armclk_rate(void)
153 {
154 	return 0;
155 }
156 
157 int board_late_init(void)
158 {
159 	rockchip_set_ethaddr();
160 	rockchip_set_serialno();
161 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
162 	setup_boot_mode();
163 #endif
164 
165 #ifdef CONFIG_DM_CHARGE_DISPLAY
166 	charge_display();
167 #endif
168 
169 #ifdef CONFIG_DRM_ROCKCHIP
170 	rockchip_show_logo();
171 #endif
172 
173 	soc_clk_dump();
174 
175 	return rk_board_late_init();
176 }
177 
178 #ifdef CONFIG_USING_KERNEL_DTB
179 #include <asm/arch/resource_img.h>
180 
181 int init_kernel_dtb(void)
182 {
183 	int ret = 0;
184 	ulong fdt_addr = 0;
185 
186 	fdt_addr = env_get_ulong("fdt_addr_r", 16, 0);
187 	if (!fdt_addr) {
188 		printf("No Found FDT Load Address.\n");
189 		return -1;
190 	}
191 
192 	ret = rockchip_read_dtb_file((void *)fdt_addr);
193 	if (ret < 0) {
194 		printf("%s dtb in resource read fail\n", __func__);
195 		return 0;
196 	}
197 
198 	of_live_build((void *)fdt_addr, (struct device_node **)&gd->of_root);
199 
200 	dm_scan_fdt((void *)fdt_addr, false);
201 
202 	gd->fdt_blob = (void *)fdt_addr;
203 
204 	/* Reserve 'reserved-memory' */
205 	ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob);
206 	if (ret)
207 		return ret;
208 
209 	return 0;
210 }
211 #endif
212 
213 void board_env_fixup(void)
214 {
215 	ulong kernel_addr_r;
216 
217 	if (gd->flags & GD_FLG_BL32_ENABLED)
218 		return;
219 
220 	/* If bl32 is disabled, maybe kernel can be load to lower address. */
221 	kernel_addr_r = env_get_ulong("kernel_addr_no_bl32_r", 16, -1);
222 	if (kernel_addr_r != -1)
223 		env_set_hex("kernel_addr_r", kernel_addr_r);
224 }
225 
226 static void early_bootrom_download(void)
227 {
228 	if (!tstc())
229 		return;
230 
231 	gd->console_evt = getc();
232 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
233 	/* ctrl+b */
234 	if (gd->console_evt == CONSOLE_EVT_CTRL_B) {
235 		printf("Enter bootrom download...");
236 		mdelay(100);
237 		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
238 		do_reset(NULL, 0, 0, NULL);
239 		printf("failed!\n");
240 	}
241 #endif
242 }
243 
244 int board_init(void)
245 {
246 	int ret;
247 
248 	board_debug_uart_init();
249 	early_bootrom_download();
250 
251 #ifdef CONFIG_USING_KERNEL_DTB
252 	init_kernel_dtb();
253 #endif
254 	/*
255 	 * pmucru isn't referenced on some platforms, so pmucru driver can't
256 	 * probe that the "assigned-clocks" is unused.
257 	 */
258 	clks_probe();
259 #ifdef CONFIG_DM_REGULATOR
260 	ret = regulators_enable_boot_on(false);
261 	if (ret)
262 		debug("%s: Cannot enable boot on regulator\n", __func__);
263 #endif
264 
265 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
266 	io_domain_init();
267 #endif
268 
269 	set_armclk_rate();
270 
271 #ifdef CONFIG_DM_DVFS
272 	dvfs_init(true);
273 #endif
274 
275 	return rk_board_init();
276 }
277 
278 int interrupt_debugger_init(void)
279 {
280 	int ret = 0;
281 
282 #ifdef CONFIG_ROCKCHIP_DEBUGGER
283 	ret = rockchip_debugger_init();
284 #endif
285 	return ret;
286 }
287 
288 #if defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808)
289 #define PINCTRL_EMMC_BUS8_PATH		"/pinctrl/emmc/emmc-bus8"
290 #define PINCTRL_EMMC_CMD_PATH		"/pinctrl/emmc/emmc-cmd"
291 #define PINCTRL_EMMC_CLK_PATH		"/pinctrl/emmc/emmc-clk"
292 #define PINCTRL_PCFG_PU_2MA_PATH	"/pinctrl/pcfg-pull-up-2ma"
293 #define MAX_ROCKCHIP_PINS_ENTRIES	12
294 
295 static int rockchip_pinctrl_cfg_fdt_fixup(const char *path, u32 new_phandle)
296 {
297 	u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
298 	const u32 *data;
299 	int i, count;
300 	int node;
301 
302 	node = fdt_path_offset(gd->fdt_blob, path);
303 	if (node < 0) {
304 		debug("%s: can't find: %s\n", __func__, path);
305 		return node;
306 	}
307 
308 	data = fdt_getprop(gd->fdt_blob, node, "rockchip,pins", &count);
309 	if (!data) {
310 		debug("%s: can't find prop \"rockchip,pins\"\n", __func__);
311 		return -ENODATA;
312 	}
313 
314 	count /= sizeof(u32);
315 	if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
316 		debug("%s: %d is over max count\n", __func__, count);
317 		return -EINVAL;
318 	}
319 
320 	for (i = 0; i < count; i++)
321 		cells[i] = data[i];
322 
323 	for (i = 0; i < (count >> 2); i++)
324 		cells[4 * i + 3] = cpu_to_fdt32(new_phandle);
325 
326 	fdt_setprop((void *)gd->fdt_blob, node, "rockchip,pins",
327 		    &cells, count * sizeof(u32));
328 
329 	return 0;
330 }
331 #endif
332 
333 int board_fdt_fixup(void *blob)
334 {
335 	int ret = 0;
336 
337 	/*
338 	 * Common fixup for DRM
339 	 */
340 #ifdef CONFIG_DRM_ROCKCHIP
341 	rockchip_display_fixup(blob);
342 #endif
343 
344 	/*
345 	 * Platform fixup:
346 	 *
347 	 * - RK3288: Recognize RK3288W by HDMI Revision ID is 0x1A;
348 	 * - RK1808: MMC strength 2mA;
349 	 */
350 #ifdef CONFIG_ROCKCHIP_RK3288
351 	if (readl(0xff980004) == 0x1A) {
352 		ret = fdt_setprop_string(blob, 0,
353 					 "compatible", "rockchip,rk3288w");
354 		if (ret)
355 			printf("fdt set compatible failed: %d\n", ret);
356 	}
357 #elif defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808)
358 	struct tag *t;
359 	u32 ph_pu_2ma;
360 
361 	t = atags_get_tag(ATAG_SOC_INFO);
362 	if (!t)
363 		return 0;
364 
365 	debug("soc=0x%x, flags=0x%x\n", t->u.soc.name, t->u.soc.flags);
366 
367 	if (t->u.soc.flags != SOC_FLAGS_ET00)
368 		return 0;
369 
370 	ph_pu_2ma = fdt_get_phandle(gd->fdt_blob,
371 		    fdt_path_offset(gd->fdt_blob, PINCTRL_PCFG_PU_2MA_PATH));
372 	if (!ph_pu_2ma) {
373 		debug("Can't find: %s\n", PINCTRL_PCFG_PU_2MA_PATH);
374 		return -EINVAL;
375 	}
376 
377 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_BUS8_PATH, ph_pu_2ma);
378 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CMD_PATH, ph_pu_2ma);
379 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CLK_PATH, ph_pu_2ma);
380 #endif
381 
382 	return ret;
383 }
384 
385 #ifdef CONFIG_ARM64_BOOT_AARCH32
386 /*
387  * Fixup MMU region attr for OP-TEE on ARMv8 CPU:
388  *
389  * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode.
390  *
391  * Command for OP-TEE:
392  *	64-bit mode: dcache is always enabled;
393  *	32-bit mode: dcache is always disabled(Due to some unknown issue);
394  *
395  * Command for U-Boot:
396  *	64-bit mode: MMU table is static defined in rkxxx.c file, all memory
397  *		     regions are mapped. That's good to match OP-TEE MMU policy.
398  *
399  *	32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where
400  *		     the OP-TEE region has been reserved, so it can not be
401  *		     mapped(i.e. dcache is disabled). That's also good to match
402  *		     OP-TEE MMU policy.
403  *
404  * For the data coherence when communication between U-Boot and OP-TEE, U-Boot
405  * should follow OP-TEE MMU policy.
406  *
407  * Here is the special:
408  *	When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while
409  *	OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE
410  *	region(but OP-TEE requires it cacheable) so we fixup here.
411  */
412 int board_initr_caches_fixup(void)
413 {
414 	struct memblock mem;
415 
416 	mem = param_parse_optee_mem();
417 	if (mem.size)
418 		mmu_set_region_dcache_behaviour(mem.base, mem.size,
419 						DCACHE_WRITEBACK);
420 	return 0;
421 }
422 #endif
423 
424 void board_quiesce_devices(void)
425 {
426 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
427 	/* Destroy atags makes next warm boot safer */
428 	atags_destroy();
429 #endif
430 }
431 
432 void enable_caches(void)
433 {
434 	icache_enable();
435 	dcache_enable();
436 }
437 
438 #ifdef CONFIG_LMB
439 /*
440  * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize".
441  * This makes lmb_alloc_base() always alloc from tail of sdram.
442  * If we don't assign it, bi_dram[0] is used by default and it may cause
443  * lmb_alloc_base() fail when bi_dram[0] range is small.
444  */
445 void board_lmb_reserve(struct lmb *lmb)
446 {
447 	u64 start, size;
448 	char bootm_low[32];
449 	char bootm_mapsize[32];
450 	int i;
451 
452 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
453 		if (!gd->bd->bi_dram[i].size)
454 			break;
455 	}
456 
457 	start = gd->bd->bi_dram[i - 1].start;
458 	size = gd->bd->bi_dram[i - 1].size;
459 
460 	/*
461 	 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+),
462 	 * otherwise "Unable to handle kernel paging request at virtual address ...".
463 	 *
464 	 * So that we hope limit highest address at 768M, but there comes the the
465 	 * problem: ramdisk is a compressed image and it expands after descompress,
466 	 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...".
467 	 *
468 	 * We make a appointment that the highest memory address is 512MB, it
469 	 * makes lmb alloc safer.
470 	 */
471 #ifndef CONFIG_ARM64
472 	if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) {
473 		start = gd->bd->bi_dram[i - 2].start;
474 		size = gd->bd->bi_dram[i - 2].size;
475 	}
476 
477 	if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M))
478 		size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start;
479 #endif
480 	sprintf(bootm_low, "0x%llx", start);
481 	sprintf(bootm_mapsize, "0x%llx", size);
482 	env_set("bootm_low", bootm_low);
483 	env_set("bootm_mapsize", bootm_mapsize);
484 }
485 #endif
486 
487 #ifdef CONFIG_BIDRAM
488 int board_bidram_reserve(struct bidram *bidram)
489 {
490 	struct memblock mem;
491 	int ret;
492 
493 	/* ATF */
494 	mem = param_parse_atf_mem();
495 	ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size);
496 	if (ret)
497 		return ret;
498 
499 	/* PSTORE/ATAGS/SHM */
500 	mem = param_parse_common_resv_mem();
501 	ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size);
502 	if (ret)
503 		return ret;
504 
505 	/* OP-TEE */
506 	mem = param_parse_optee_mem();
507 	ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size);
508 	if (ret)
509 		return ret;
510 
511 	return 0;
512 }
513 
514 parse_fn_t board_bidram_parse_fn(void)
515 {
516 	return param_parse_ddr_mem;
517 }
518 #endif
519 
520 #ifdef CONFIG_ROCKCHIP_AMP
521 void cpu_secondary_init_r(void)
522 {
523 	amp_cpus_on();
524 }
525 #endif
526 
527 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
528     defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
529 int board_init_f_init_serial(void)
530 {
531 	struct tag *t = atags_get_tag(ATAG_SERIAL);
532 
533 	if (t) {
534 		gd->serial.using_pre_serial = t->u.serial.enable;
535 		gd->serial.addr = t->u.serial.addr;
536 		gd->serial.baudrate = t->u.serial.baudrate;
537 		gd->serial.id = t->u.serial.id;
538 
539 		debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n",
540 		      __func__, gd->serial.using_pre_serial,
541 		      gd->serial.addr, gd->serial.baudrate,
542 		      gd->serial.id);
543 	}
544 
545 	return 0;
546 }
547 #endif
548 
549 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
550 #include <fdt_support.h>
551 #include <usb.h>
552 #include <usb/dwc2_udc.h>
553 
554 static struct dwc2_plat_otg_data otg_data = {
555 	.rx_fifo_sz	= 512,
556 	.np_tx_fifo_sz	= 16,
557 	.tx_fifo_sz	= 128,
558 };
559 
560 int board_usb_init(int index, enum usb_init_type init)
561 {
562 	int node;
563 	fdt_addr_t addr;
564 	const fdt32_t *reg;
565 	const void *blob = gd->fdt_blob;
566 
567 	/* find the usb_otg node */
568 	node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
569 
570 retry:
571 	if (node > 0) {
572 		reg = fdt_getprop(blob, node, "reg", NULL);
573 		if (!reg)
574 			return -EINVAL;
575 
576 		addr = fdt_translate_address(blob, node, reg);
577 		if (addr == OF_BAD_ADDR) {
578 			pr_err("Not found usb_otg address\n");
579 			return -EINVAL;
580 		}
581 
582 #if defined(CONFIG_ROCKCHIP_RK3288)
583 		if (addr != 0xff580000) {
584 			node = fdt_node_offset_by_compatible(blob, node,
585 							     "snps,dwc2");
586 			goto retry;
587 		}
588 #endif
589 	} else {
590 		/*
591 		 * With kernel dtb support, rk3288 dwc2 otg node
592 		 * use the rockchip legacy dwc2 driver "dwc_otg_310"
593 		 * with the compatible "rockchip,rk3288_usb20_otg",
594 		 * and rk3368 also use the "dwc_otg_310" driver with
595 		 * the compatible "rockchip,rk3368-usb".
596 		 */
597 #if defined(CONFIG_ROCKCHIP_RK3288)
598 		node = fdt_node_offset_by_compatible(blob, -1,
599 				"rockchip,rk3288_usb20_otg");
600 #elif defined(CONFIG_ROCKCHIP_RK3368)
601 		node = fdt_node_offset_by_compatible(blob, -1,
602 				"rockchip,rk3368-usb");
603 #endif
604 		if (node > 0) {
605 			goto retry;
606 		} else {
607 			pr_err("Not found usb_otg device\n");
608 			return -ENODEV;
609 		}
610 	}
611 
612 	otg_data.regs_otg = (uintptr_t)addr;
613 
614 	return dwc2_udc_probe(&otg_data);
615 }
616 
617 int board_usb_cleanup(int index, enum usb_init_type init)
618 {
619 	return 0;
620 }
621 #endif
622