xref: /rk3399_rockchip-uboot/arch/arm/mach-rockchip/board.c (revision ed73b76733ce7cd243da2ebec965b0e1fca8924d) 
1 /*
2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 #include <common.h>
7 #include <clk.h>
8 #include <bidram.h>
9 #include <dm.h>
10 #include <debug_uart.h>
11 #include <memblk.h>
12 #include <ram.h>
13 #include <syscon.h>
14 #include <sysmem.h>
15 #include <asm/io.h>
16 #include <asm/arch/vendor.h>
17 #include <misc.h>
18 #include <asm/gpio.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/periph.h>
21 #include <asm/arch/boot_mode.h>
22 #include <asm/arch/rk_atags.h>
23 #include <asm/arch/param.h>
24 #ifdef CONFIG_DM_CHARGE_DISPLAY
25 #include <power/charge_display.h>
26 #endif
27 #ifdef CONFIG_DM_DVFS
28 #include <dvfs.h>
29 #endif
30 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
31 #include <io-domain.h>
32 #endif
33 #ifdef CONFIG_DM_REGULATOR
34 #include <power/regulator.h>
35 #endif
36 #ifdef CONFIG_DRM_ROCKCHIP
37 #include <video_rockchip.h>
38 #endif
39 #ifdef CONFIG_ROCKCHIP_DEBUGGER
40 #include <rockchip_debugger.h>
41 #endif
42 #include <of_live.h>
43 #include <dm/root.h>
44 #include <console.h>
45 
46 DECLARE_GLOBAL_DATA_PTR;
47 /* define serialno max length, the max length is 512 Bytes
48  * The remaining bytes are used to ensure that the first 512 bytes
49  * are valid when executing 'env_set("serial#", value)'.
50  */
51 #define VENDOR_SN_MAX	513
52 #define CPUID_LEN       0x10
53 #define CPUID_OFF       0x7
54 
55 static int rockchip_set_ethaddr(void)
56 {
57 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
58 	int ret;
59 	u8 ethaddr[ARP_HLEN];
60 	char buf[ARP_HLEN_ASCII + 1];
61 
62 	ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr));
63 	if (ret > 0 && is_valid_ethaddr(ethaddr)) {
64 		sprintf(buf, "%pM", ethaddr);
65 		env_set("ethaddr", buf);
66 	}
67 #endif
68 	return 0;
69 }
70 
71 static int rockchip_set_serialno(void)
72 {
73 	char serialno_str[VENDOR_SN_MAX];
74 	int ret = 0, i;
75 	u8 cpuid[CPUID_LEN] = {0};
76 	u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2];
77 	u64 serialno;
78 
79 	/* Read serial number from vendor storage part */
80 	memset(serialno_str, 0, VENDOR_SN_MAX);
81 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
82 	ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1));
83 	if (ret > 0) {
84 		env_set("serial#", serialno_str);
85 	} else {
86 #endif
87 #ifdef CONFIG_ROCKCHIP_EFUSE
88 		struct udevice *dev;
89 
90 		/* retrieve the device */
91 		ret = uclass_get_device_by_driver(UCLASS_MISC,
92 						  DM_GET_DRIVER(rockchip_efuse), &dev);
93 		if (ret) {
94 			printf("%s: could not find efuse device\n", __func__);
95 			return ret;
96 		}
97 		/* read the cpu_id range from the efuses */
98 		ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid));
99 		if (ret) {
100 			printf("%s: reading cpuid from the efuses failed\n", __func__);
101 			return ret;
102 		}
103 #else
104 		/* generate random cpuid */
105 		for (i = 0; i < CPUID_LEN; i++) {
106 			cpuid[i] = (u8)(rand());
107 		}
108 #endif
109 		/* Generate the serial number based on CPU ID */
110 		for (i = 0; i < 8; i++) {
111 			low[i] = cpuid[1 + (i << 1)];
112 			high[i] = cpuid[i << 1];
113 		}
114 		serialno = crc32_no_comp(0, low, 8);
115 		serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
116 		snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno);
117 
118 		env_set("serial#", serialno_str);
119 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
120 	}
121 #endif
122 	return ret;
123 }
124 
125 #if defined(CONFIG_USB_FUNCTION_FASTBOOT)
126 int fb_set_reboot_flag(void)
127 {
128 	printf("Setting reboot to fastboot flag ...\n");
129 	/* Set boot mode to fastboot */
130 	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
131 
132 	return 0;
133 }
134 #endif
135 
136 __weak int rk_board_init(void)
137 {
138 	return 0;
139 }
140 
141 __weak int rk_board_late_init(void)
142 {
143 	return 0;
144 }
145 
146 __weak int soc_clk_dump(void)
147 {
148 	return 0;
149 }
150 
151 __weak int set_armclk_rate(void)
152 {
153 	return 0;
154 }
155 
156 int board_late_init(void)
157 {
158 	rockchip_set_ethaddr();
159 	rockchip_set_serialno();
160 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
161 	setup_boot_mode();
162 #endif
163 
164 #ifdef CONFIG_DM_CHARGE_DISPLAY
165 	charge_display();
166 #endif
167 
168 #ifdef CONFIG_DRM_ROCKCHIP
169 	rockchip_show_logo();
170 #endif
171 
172 	soc_clk_dump();
173 
174 	return rk_board_late_init();
175 }
176 
177 #ifdef CONFIG_USING_KERNEL_DTB
178 #include <asm/arch/resource_img.h>
179 
180 int init_kernel_dtb(void)
181 {
182 	int ret = 0;
183 	ulong fdt_addr = 0;
184 
185 	fdt_addr = env_get_ulong("fdt_addr_r", 16, 0);
186 	if (!fdt_addr) {
187 		printf("No Found FDT Load Address.\n");
188 		return -1;
189 	}
190 
191 	ret = rockchip_read_dtb_file((void *)fdt_addr);
192 	if (ret < 0) {
193 		printf("%s dtb in resource read fail\n", __func__);
194 		return 0;
195 	}
196 
197 	of_live_build((void *)fdt_addr, (struct device_node **)&gd->of_root);
198 
199 	dm_scan_fdt((void *)fdt_addr, false);
200 
201 	gd->fdt_blob = (void *)fdt_addr;
202 
203 	/* Reserve 'reserved-memory' */
204 	ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob);
205 	if (ret)
206 		return ret;
207 
208 	return 0;
209 }
210 #endif
211 
212 void board_env_fixup(void)
213 {
214 	ulong kernel_addr_r;
215 
216 	if (gd->flags & GD_FLG_BL32_ENABLED)
217 		return;
218 
219 	/* If bl32 is disabled, maybe kernel can be load to lower address. */
220 	kernel_addr_r = env_get_ulong("kernel_addr_no_bl32_r", 16, -1);
221 	if (kernel_addr_r != -1)
222 		env_set_hex("kernel_addr_r", kernel_addr_r);
223 }
224 
225 static void early_bootrom_download(void)
226 {
227 	if (!tstc())
228 		return;
229 
230 	gd->console_evt = getc();
231 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
232 	/* ctrl+b */
233 	if (gd->console_evt == CONSOLE_EVT_CTRL_B) {
234 		printf("Enter bootrom download...");
235 		mdelay(100);
236 		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
237 		do_reset(NULL, 0, 0, NULL);
238 		printf("failed!\n");
239 	}
240 #endif
241 }
242 
243 int board_init(void)
244 {
245 	int ret;
246 
247 	board_debug_uart_init();
248 	early_bootrom_download();
249 
250 #ifdef CONFIG_USING_KERNEL_DTB
251 	init_kernel_dtb();
252 #endif
253 	/*
254 	 * pmucru isn't referenced on some platforms, so pmucru driver can't
255 	 * probe that the "assigned-clocks" is unused.
256 	 */
257 	clks_probe();
258 #ifdef CONFIG_DM_REGULATOR
259 	ret = regulators_enable_boot_on(false);
260 	if (ret)
261 		debug("%s: Cannot enable boot on regulator\n", __func__);
262 #endif
263 
264 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
265 	io_domain_init();
266 #endif
267 
268 	set_armclk_rate();
269 
270 #ifdef CONFIG_DM_DVFS
271 	dvfs_init(true);
272 #endif
273 
274 	return rk_board_init();
275 }
276 
277 int interrupt_debugger_init(void)
278 {
279 	int ret = 0;
280 
281 #ifdef CONFIG_ROCKCHIP_DEBUGGER
282 	ret = rockchip_debugger_init();
283 #endif
284 	return ret;
285 }
286 
287 #if defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808)
288 #define PINCTRL_EMMC_BUS8_PATH		"/pinctrl/emmc/emmc-bus8"
289 #define PINCTRL_EMMC_CMD_PATH		"/pinctrl/emmc/emmc-cmd"
290 #define PINCTRL_EMMC_CLK_PATH		"/pinctrl/emmc/emmc-clk"
291 #define PINCTRL_PCFG_PU_2MA_PATH	"/pinctrl/pcfg-pull-up-2ma"
292 #define MAX_ROCKCHIP_PINS_ENTRIES	12
293 
294 static int rockchip_pinctrl_cfg_fdt_fixup(const char *path, u32 new_phandle)
295 {
296 	u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
297 	const u32 *data;
298 	int i, count;
299 	int node;
300 
301 	node = fdt_path_offset(gd->fdt_blob, path);
302 	if (node < 0) {
303 		debug("%s: can't find: %s\n", __func__, path);
304 		return node;
305 	}
306 
307 	data = fdt_getprop(gd->fdt_blob, node, "rockchip,pins", &count);
308 	if (!data) {
309 		debug("%s: can't find prop \"rockchip,pins\"\n", __func__);
310 		return -ENODATA;
311 	}
312 
313 	count /= sizeof(u32);
314 	if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
315 		debug("%s: %d is over max count\n", __func__, count);
316 		return -EINVAL;
317 	}
318 
319 	for (i = 0; i < count; i++)
320 		cells[i] = data[i];
321 
322 	for (i = 0; i < (count >> 2); i++)
323 		cells[4 * i + 3] = cpu_to_fdt32(new_phandle);
324 
325 	fdt_setprop((void *)gd->fdt_blob, node, "rockchip,pins",
326 		    &cells, count * sizeof(u32));
327 
328 	return 0;
329 }
330 #endif
331 
332 int board_fdt_fixup(void *blob)
333 {
334 	int ret = 0;
335 
336 	/*
337 	 * Common fixup for DRM
338 	 */
339 #ifdef CONFIG_DRM_ROCKCHIP
340 	rockchip_display_fixup(blob);
341 #endif
342 
343 	/*
344 	 * Platform fixup:
345 	 *
346 	 * - RK3288: Recognize RK3288W by HDMI Revision ID is 0x1A;
347 	 * - RK1808: MMC strength 2mA;
348 	 */
349 #ifdef CONFIG_ROCKCHIP_RK3288
350 	if (readl(0xff980004) == 0x1A) {
351 		ret = fdt_setprop_string(blob, 0,
352 					 "compatible", "rockchip,rk3288w");
353 		if (ret)
354 			printf("fdt set compatible failed: %d\n", ret);
355 	}
356 #elif defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808)
357 	struct tag *t;
358 	u32 ph_pu_2ma;
359 
360 	t = atags_get_tag(ATAG_SOC_INFO);
361 	if (!t)
362 		return 0;
363 
364 	debug("soc=0x%x, flags=0x%x\n", t->u.soc.name, t->u.soc.flags);
365 
366 	if (t->u.soc.flags != SOC_FLAGS_ET00)
367 		return 0;
368 
369 	ph_pu_2ma = fdt_get_phandle(gd->fdt_blob,
370 		    fdt_path_offset(gd->fdt_blob, PINCTRL_PCFG_PU_2MA_PATH));
371 	if (!ph_pu_2ma) {
372 		debug("Can't find: %s\n", PINCTRL_PCFG_PU_2MA_PATH);
373 		return -EINVAL;
374 	}
375 
376 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_BUS8_PATH, ph_pu_2ma);
377 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CMD_PATH, ph_pu_2ma);
378 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CLK_PATH, ph_pu_2ma);
379 #endif
380 
381 	return ret;
382 }
383 
384 #ifdef CONFIG_ARM64_BOOT_AARCH32
385 /*
386  * Fixup MMU region attr for OP-TEE on ARMv8 CPU:
387  *
388  * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode.
389  *
390  * Command for OP-TEE:
391  *	64-bit mode: dcache is always enabled;
392  *	32-bit mode: dcache is always disabled(Due to some unknown issue);
393  *
394  * Command for U-Boot:
395  *	64-bit mode: MMU table is static defined in rkxxx.c file, all memory
396  *		     regions are mapped. That's good to match OP-TEE MMU policy.
397  *
398  *	32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where
399  *		     the OP-TEE region has been reserved, so it can not be
400  *		     mapped(i.e. dcache is disabled). That's also good to match
401  *		     OP-TEE MMU policy.
402  *
403  * For the data coherence when communication between U-Boot and OP-TEE, U-Boot
404  * should follow OP-TEE MMU policy.
405  *
406  * Here is the special:
407  *	When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while
408  *	OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE
409  *	region(but OP-TEE requires it cacheable) so we fixup here.
410  */
411 int board_initr_caches_fixup(void)
412 {
413 	struct memblock mem;
414 
415 	mem = param_parse_optee_mem();
416 	if (mem.size)
417 		mmu_set_region_dcache_behaviour(mem.base, mem.size,
418 						DCACHE_WRITEBACK);
419 	return 0;
420 }
421 #endif
422 
423 void board_quiesce_devices(void)
424 {
425 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
426 	/* Destroy atags makes next warm boot safer */
427 	atags_destroy();
428 #endif
429 }
430 
431 void enable_caches(void)
432 {
433 	icache_enable();
434 	dcache_enable();
435 }
436 
437 #ifdef CONFIG_LMB
438 /*
439  * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize".
440  * This makes lmb_alloc_base() always alloc from tail of sdram.
441  * If we don't assign it, bi_dram[0] is used by default and it may cause
442  * lmb_alloc_base() fail when bi_dram[0] range is small.
443  */
444 void board_lmb_reserve(struct lmb *lmb)
445 {
446 	u64 start, size;
447 	char bootm_low[32];
448 	char bootm_mapsize[32];
449 	int i;
450 
451 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
452 		if (!gd->bd->bi_dram[i].size)
453 			break;
454 	}
455 
456 	start = gd->bd->bi_dram[i - 1].start;
457 	size = gd->bd->bi_dram[i - 1].size;
458 
459 	/*
460 	 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+),
461 	 * otherwise "Unable to handle kernel paging request at virtual address ...".
462 	 *
463 	 * So that we hope limit highest address at 768M, but there comes the the
464 	 * problem: ramdisk is a compressed image and it expands after descompress,
465 	 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...".
466 	 *
467 	 * We make a appointment that the highest memory address is 512MB, it
468 	 * makes lmb alloc safer.
469 	 */
470 #ifndef CONFIG_ARM64
471 	if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) {
472 		start = gd->bd->bi_dram[i - 2].start;
473 		size = gd->bd->bi_dram[i - 2].size;
474 	}
475 
476 	if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M))
477 		size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start;
478 #endif
479 	sprintf(bootm_low, "0x%llx", start);
480 	sprintf(bootm_mapsize, "0x%llx", size);
481 	env_set("bootm_low", bootm_low);
482 	env_set("bootm_mapsize", bootm_mapsize);
483 }
484 #endif
485 
486 #ifdef CONFIG_BIDRAM
487 int board_bidram_reserve(struct bidram *bidram)
488 {
489 	struct memblock mem;
490 	int ret;
491 
492 	/* ATF */
493 	mem = param_parse_atf_mem();
494 	ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size);
495 	if (ret)
496 		return ret;
497 
498 	/* PSTORE/ATAGS/SHM */
499 	mem = param_parse_common_resv_mem();
500 	ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size);
501 	if (ret)
502 		return ret;
503 
504 	/* OP-TEE */
505 	mem = param_parse_optee_mem();
506 	ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size);
507 	if (ret)
508 		return ret;
509 
510 	return 0;
511 }
512 
513 parse_fn_t board_bidram_parse_fn(void)
514 {
515 	return param_parse_ddr_mem;
516 }
517 #endif
518 
519 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
520     defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
521 int board_init_f_init_serial(void)
522 {
523 	struct tag *t = atags_get_tag(ATAG_SERIAL);
524 
525 	if (t) {
526 		gd->serial.using_pre_serial = t->u.serial.enable;
527 		gd->serial.addr = t->u.serial.addr;
528 		gd->serial.baudrate = t->u.serial.baudrate;
529 		gd->serial.id = t->u.serial.id;
530 
531 		debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n",
532 		      __func__, gd->serial.using_pre_serial,
533 		      gd->serial.addr, gd->serial.baudrate,
534 		      gd->serial.id);
535 	}
536 
537 	return 0;
538 }
539 #endif
540 
541 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
542 #include <fdt_support.h>
543 #include <usb.h>
544 #include <usb/dwc2_udc.h>
545 
546 static struct dwc2_plat_otg_data otg_data = {
547 	.rx_fifo_sz	= 512,
548 	.np_tx_fifo_sz	= 16,
549 	.tx_fifo_sz	= 128,
550 };
551 
552 int board_usb_init(int index, enum usb_init_type init)
553 {
554 	int node;
555 	fdt_addr_t addr;
556 	const fdt32_t *reg;
557 	const void *blob = gd->fdt_blob;
558 
559 	/* find the usb_otg node */
560 	node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
561 
562 retry:
563 	if (node > 0) {
564 		reg = fdt_getprop(blob, node, "reg", NULL);
565 		if (!reg)
566 			return -EINVAL;
567 
568 		addr = fdt_translate_address(blob, node, reg);
569 		if (addr == OF_BAD_ADDR) {
570 			pr_err("Not found usb_otg address\n");
571 			return -EINVAL;
572 		}
573 
574 #if defined(CONFIG_ROCKCHIP_RK3288)
575 		if (addr != 0xff580000) {
576 			node = fdt_node_offset_by_compatible(blob, node,
577 							     "snps,dwc2");
578 			goto retry;
579 		}
580 #endif
581 	} else {
582 		/*
583 		 * With kernel dtb support, rk3288 dwc2 otg node
584 		 * use the rockchip legacy dwc2 driver "dwc_otg_310"
585 		 * with the compatible "rockchip,rk3288_usb20_otg",
586 		 * and rk3368 also use the "dwc_otg_310" driver with
587 		 * the compatible "rockchip,rk3368-usb".
588 		 */
589 #if defined(CONFIG_ROCKCHIP_RK3288)
590 		node = fdt_node_offset_by_compatible(blob, -1,
591 				"rockchip,rk3288_usb20_otg");
592 #elif defined(CONFIG_ROCKCHIP_RK3368)
593 		node = fdt_node_offset_by_compatible(blob, -1,
594 				"rockchip,rk3368-usb");
595 #endif
596 		if (node > 0) {
597 			goto retry;
598 		} else {
599 			pr_err("Not found usb_otg device\n");
600 			return -ENODEV;
601 		}
602 	}
603 
604 	otg_data.regs_otg = (uintptr_t)addr;
605 
606 	return dwc2_udc_probe(&otg_data);
607 }
608 
609 int board_usb_cleanup(int index, enum usb_init_type init)
610 {
611 	return 0;
612 }
613 #endif
614