xref: /rk3399_rockchip-uboot/arch/arm/mach-rockchip/board.c (revision e8c34540a61ba8ec3ef255e3e8a72e7d3409f5f5) 
1 /*
2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 #include <common.h>
7 #include <amp.h>
8 #include <clk.h>
9 #include <bidram.h>
10 #include <dm.h>
11 #include <debug_uart.h>
12 #include <memblk.h>
13 #include <ram.h>
14 #include <syscon.h>
15 #include <sysmem.h>
16 #include <asm/io.h>
17 #include <asm/arch/vendor.h>
18 #include <misc.h>
19 #include <asm/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/periph.h>
23 #include <asm/arch/boot_mode.h>
24 #include <asm/arch/hotkey.h>
25 #include <asm/arch/rk_atags.h>
26 #include <asm/arch/param.h>
27 #ifdef CONFIG_DM_CHARGE_DISPLAY
28 #include <power/charge_display.h>
29 #endif
30 #ifdef CONFIG_DM_DVFS
31 #include <dvfs.h>
32 #endif
33 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
34 #include <io-domain.h>
35 #endif
36 #ifdef CONFIG_DM_REGULATOR
37 #include <power/regulator.h>
38 #endif
39 #ifdef CONFIG_DRM_ROCKCHIP
40 #include <video_rockchip.h>
41 #endif
42 #ifdef CONFIG_ROCKCHIP_DEBUGGER
43 #include <rockchip_debugger.h>
44 #endif
45 #include <of_live.h>
46 #include <dm/root.h>
47 #include <console.h>
48 
49 DECLARE_GLOBAL_DATA_PTR;
50 /* define serialno max length, the max length is 512 Bytes
51  * The remaining bytes are used to ensure that the first 512 bytes
52  * are valid when executing 'env_set("serial#", value)'.
53  */
54 #define VENDOR_SN_MAX	513
55 #define CPUID_LEN       0x10
56 #define CPUID_OFF       0x7
57 
58 static int rockchip_set_ethaddr(void)
59 {
60 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
61 	int ret;
62 	u8 ethaddr[ARP_HLEN];
63 	char buf[ARP_HLEN_ASCII + 1];
64 
65 	ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr));
66 	if (ret > 0 && is_valid_ethaddr(ethaddr)) {
67 		sprintf(buf, "%pM", ethaddr);
68 		env_set("ethaddr", buf);
69 	}
70 #endif
71 	return 0;
72 }
73 
74 static int rockchip_set_serialno(void)
75 {
76 	char serialno_str[VENDOR_SN_MAX];
77 	int ret = 0, i;
78 	u8 cpuid[CPUID_LEN] = {0};
79 	u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2];
80 	u64 serialno;
81 
82 	/* Read serial number from vendor storage part */
83 	memset(serialno_str, 0, VENDOR_SN_MAX);
84 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
85 	ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1));
86 	if (ret > 0) {
87 		env_set("serial#", serialno_str);
88 	} else {
89 #endif
90 #ifdef CONFIG_ROCKCHIP_EFUSE
91 		struct udevice *dev;
92 
93 		/* retrieve the device */
94 		ret = uclass_get_device_by_driver(UCLASS_MISC,
95 						  DM_GET_DRIVER(rockchip_efuse), &dev);
96 		if (ret) {
97 			printf("%s: could not find efuse device\n", __func__);
98 			return ret;
99 		}
100 		/* read the cpu_id range from the efuses */
101 		ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid));
102 		if (ret) {
103 			printf("%s: reading cpuid from the efuses failed\n", __func__);
104 			return ret;
105 		}
106 #else
107 		/* generate random cpuid */
108 		for (i = 0; i < CPUID_LEN; i++) {
109 			cpuid[i] = (u8)(rand());
110 		}
111 #endif
112 		/* Generate the serial number based on CPU ID */
113 		for (i = 0; i < 8; i++) {
114 			low[i] = cpuid[1 + (i << 1)];
115 			high[i] = cpuid[i << 1];
116 		}
117 		serialno = crc32_no_comp(0, low, 8);
118 		serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
119 		snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno);
120 
121 		env_set("serial#", serialno_str);
122 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
123 	}
124 #endif
125 	return ret;
126 }
127 
128 #if defined(CONFIG_USB_FUNCTION_FASTBOOT)
129 int fb_set_reboot_flag(void)
130 {
131 	printf("Setting reboot to fastboot flag ...\n");
132 	/* Set boot mode to fastboot */
133 	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
134 
135 	return 0;
136 }
137 #endif
138 
139 __weak int rk_board_init(void)
140 {
141 	return 0;
142 }
143 
144 __weak int rk_board_late_init(void)
145 {
146 	return 0;
147 }
148 
149 __weak int soc_clk_dump(void)
150 {
151 	return 0;
152 }
153 
154 __weak int set_armclk_rate(void)
155 {
156 	return 0;
157 }
158 
159 int board_late_init(void)
160 {
161 	rockchip_set_ethaddr();
162 	rockchip_set_serialno();
163 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
164 	setup_boot_mode();
165 #endif
166 
167 #ifdef CONFIG_DM_CHARGE_DISPLAY
168 	charge_display();
169 #endif
170 
171 #ifdef CONFIG_DRM_ROCKCHIP
172 	rockchip_show_logo();
173 #endif
174 
175 	soc_clk_dump();
176 
177 	return rk_board_late_init();
178 }
179 
180 #ifdef CONFIG_USING_KERNEL_DTB
181 #include <asm/arch/resource_img.h>
182 
183 int init_kernel_dtb(void)
184 {
185 	int ret = 0;
186 	ulong fdt_addr = 0;
187 
188 	fdt_addr = env_get_ulong("fdt_addr_r", 16, 0);
189 	if (!fdt_addr) {
190 		printf("No Found FDT Load Address.\n");
191 		return -1;
192 	}
193 
194 	ret = rockchip_read_dtb_file((void *)fdt_addr);
195 	if (ret < 0) {
196 		printf("%s dtb in resource read fail\n", __func__);
197 		return 0;
198 	}
199 
200 	of_live_build((void *)fdt_addr, (struct device_node **)&gd->of_root);
201 
202 	dm_scan_fdt((void *)fdt_addr, false);
203 
204 	gd->fdt_blob = (void *)fdt_addr;
205 
206 	/* Reserve 'reserved-memory' */
207 	ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob);
208 	if (ret)
209 		return ret;
210 
211 	return 0;
212 }
213 #endif
214 
215 void board_env_fixup(void)
216 {
217 	char *addr_r;
218 #ifdef ENV_MEM_LAYOUT_SETTINGS1
219 	const char *env_addr0[] = {
220 		"scriptaddr", "pxefile_addr_r",
221 		"fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r",
222 	};
223 	const char *env_addr1[] = {
224 		"scriptaddr1", "pxefile_addr1_r",
225 		"fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r",
226 	};
227 	int i;
228 
229 	/* 128M is a typical ram size for most platform, so as default here */
230 	if (gd->ram_size <= SZ_128M) {
231 		/* Replace orignal xxx_addr_r */
232 		for (i = 0; i < ARRAY_SIZE(env_addr1); i++) {
233 			addr_r = env_get(env_addr1[i]);
234 			if (addr_r)
235 				env_set(env_addr0[i], addr_r);
236 		}
237 	}
238 #endif
239 	/* If bl32 is disabled, maybe kernel can be load to lower address. */
240 	if (!(gd->flags & GD_FLG_BL32_ENABLED)) {
241 		addr_r = env_get("kernel_addr_no_bl32_r");
242 		if (addr_r)
243 			env_set("kernel_addr_r", addr_r);
244 	}
245 }
246 
247 static void early_bootrom_download(void)
248 {
249 	if (!tstc())
250 		return;
251 
252 	gd->console_evt = getc();
253 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
254 	/* ctrl+b */
255 	if (is_hotkey(HK_BROM_DNL)) {
256 		printf("Enter bootrom download...");
257 		flushc();
258 		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
259 		do_reset(NULL, 0, 0, NULL);
260 		printf("failed!\n");
261 	}
262 #endif
263 }
264 
265 int board_init(void)
266 {
267 	int ret;
268 
269 	board_debug_uart_init();
270 	early_bootrom_download();
271 
272 #ifdef CONFIG_USING_KERNEL_DTB
273 	init_kernel_dtb();
274 #endif
275 	/*
276 	 * pmucru isn't referenced on some platforms, so pmucru driver can't
277 	 * probe that the "assigned-clocks" is unused.
278 	 */
279 	clks_probe();
280 #ifdef CONFIG_DM_REGULATOR
281 	ret = regulators_enable_boot_on(false);
282 	if (ret)
283 		debug("%s: Cannot enable boot on regulator\n", __func__);
284 #endif
285 
286 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
287 	io_domain_init();
288 #endif
289 
290 	set_armclk_rate();
291 
292 #ifdef CONFIG_DM_DVFS
293 	dvfs_init(true);
294 #endif
295 
296 	return rk_board_init();
297 }
298 
299 int interrupt_debugger_init(void)
300 {
301 	int ret = 0;
302 
303 #ifdef CONFIG_ROCKCHIP_DEBUGGER
304 	ret = rockchip_debugger_init();
305 #endif
306 	return ret;
307 }
308 
309 #if defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808)
310 #define PINCTRL_EMMC_BUS8_PATH		"/pinctrl/emmc/emmc-bus8"
311 #define PINCTRL_EMMC_CMD_PATH		"/pinctrl/emmc/emmc-cmd"
312 #define PINCTRL_EMMC_CLK_PATH		"/pinctrl/emmc/emmc-clk"
313 #define PINCTRL_PCFG_PU_2MA_PATH	"/pinctrl/pcfg-pull-up-2ma"
314 #define MAX_ROCKCHIP_PINS_ENTRIES	12
315 
316 static int rockchip_pinctrl_cfg_fdt_fixup(const char *path, u32 new_phandle)
317 {
318 	u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
319 	const u32 *data;
320 	int i, count;
321 	int node;
322 
323 	node = fdt_path_offset(gd->fdt_blob, path);
324 	if (node < 0) {
325 		debug("%s: can't find: %s\n", __func__, path);
326 		return node;
327 	}
328 
329 	data = fdt_getprop(gd->fdt_blob, node, "rockchip,pins", &count);
330 	if (!data) {
331 		debug("%s: can't find prop \"rockchip,pins\"\n", __func__);
332 		return -ENODATA;
333 	}
334 
335 	count /= sizeof(u32);
336 	if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
337 		debug("%s: %d is over max count\n", __func__, count);
338 		return -EINVAL;
339 	}
340 
341 	for (i = 0; i < count; i++)
342 		cells[i] = data[i];
343 
344 	for (i = 0; i < (count >> 2); i++)
345 		cells[4 * i + 3] = cpu_to_fdt32(new_phandle);
346 
347 	fdt_setprop((void *)gd->fdt_blob, node, "rockchip,pins",
348 		    &cells, count * sizeof(u32));
349 
350 	return 0;
351 }
352 #endif
353 
354 int board_fdt_fixup(void *blob)
355 {
356 	int ret = 0;
357 
358 	/*
359 	 * Common fixup for DRM
360 	 */
361 #ifdef CONFIG_DRM_ROCKCHIP
362 	rockchip_display_fixup(blob);
363 #endif
364 
365 	/*
366 	 * Platform fixup:
367 	 *
368 	 * - RK3288: Recognize RK3288W by HDMI Revision ID is 0x1A;
369 	 * - RK1808: MMC strength 2mA;
370 	 */
371 #ifdef CONFIG_ROCKCHIP_RK3288
372 	if (soc_is_rk3288w()) {
373 		ret = fdt_setprop_string(blob, 0,
374 					 "compatible", "rockchip,rk3288w");
375 		if (ret)
376 			printf("fdt set compatible failed: %d\n", ret);
377 	}
378 #elif defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808)
379 	struct tag *t;
380 	u32 ph_pu_2ma;
381 
382 	t = atags_get_tag(ATAG_SOC_INFO);
383 	if (!t)
384 		return 0;
385 
386 	debug("soc=0x%x, flags=0x%x\n", t->u.soc.name, t->u.soc.flags);
387 
388 	if (t->u.soc.flags != SOC_FLAGS_ET00)
389 		return 0;
390 
391 	ph_pu_2ma = fdt_get_phandle(gd->fdt_blob,
392 		    fdt_path_offset(gd->fdt_blob, PINCTRL_PCFG_PU_2MA_PATH));
393 	if (!ph_pu_2ma) {
394 		debug("Can't find: %s\n", PINCTRL_PCFG_PU_2MA_PATH);
395 		return -EINVAL;
396 	}
397 
398 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_BUS8_PATH, ph_pu_2ma);
399 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CMD_PATH, ph_pu_2ma);
400 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CLK_PATH, ph_pu_2ma);
401 #endif
402 
403 	return ret;
404 }
405 
406 #ifdef CONFIG_ARM64_BOOT_AARCH32
407 /*
408  * Fixup MMU region attr for OP-TEE on ARMv8 CPU:
409  *
410  * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode.
411  *
412  * Command for OP-TEE:
413  *	64-bit mode: dcache is always enabled;
414  *	32-bit mode: dcache is always disabled(Due to some unknown issue);
415  *
416  * Command for U-Boot:
417  *	64-bit mode: MMU table is static defined in rkxxx.c file, all memory
418  *		     regions are mapped. That's good to match OP-TEE MMU policy.
419  *
420  *	32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where
421  *		     the OP-TEE region has been reserved, so it can not be
422  *		     mapped(i.e. dcache is disabled). That's also good to match
423  *		     OP-TEE MMU policy.
424  *
425  * For the data coherence when communication between U-Boot and OP-TEE, U-Boot
426  * should follow OP-TEE MMU policy.
427  *
428  * Here is the special:
429  *	When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while
430  *	OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE
431  *	region(but OP-TEE requires it cacheable) so we fixup here.
432  */
433 int board_initr_caches_fixup(void)
434 {
435 	struct memblock mem;
436 
437 	mem = param_parse_optee_mem();
438 	if (mem.size)
439 		mmu_set_region_dcache_behaviour(mem.base, mem.size,
440 						DCACHE_WRITEBACK);
441 	return 0;
442 }
443 #endif
444 
445 void board_quiesce_devices(void)
446 {
447 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
448 	/* Destroy atags makes next warm boot safer */
449 	atags_destroy();
450 #endif
451 
452 #if defined(CONFIG_CONSOLE_RECORD)
453 	/* Print record console data */
454 	console_record_print_purge();
455 #endif
456 }
457 
458 void enable_caches(void)
459 {
460 	icache_enable();
461 	dcache_enable();
462 }
463 
464 #ifdef CONFIG_LMB
465 /*
466  * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize".
467  * This makes lmb_alloc_base() always alloc from tail of sdram.
468  * If we don't assign it, bi_dram[0] is used by default and it may cause
469  * lmb_alloc_base() fail when bi_dram[0] range is small.
470  */
471 void board_lmb_reserve(struct lmb *lmb)
472 {
473 	u64 start, size;
474 	char bootm_low[32];
475 	char bootm_mapsize[32];
476 	int i;
477 
478 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
479 		if (!gd->bd->bi_dram[i].size)
480 			break;
481 	}
482 
483 	start = gd->bd->bi_dram[i - 1].start;
484 	size = gd->bd->bi_dram[i - 1].size;
485 
486 	/*
487 	 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+),
488 	 * otherwise "Unable to handle kernel paging request at virtual address ...".
489 	 *
490 	 * So that we hope limit highest address at 768M, but there comes the the
491 	 * problem: ramdisk is a compressed image and it expands after descompress,
492 	 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...".
493 	 *
494 	 * We make a appointment that the highest memory address is 512MB, it
495 	 * makes lmb alloc safer.
496 	 */
497 #ifndef CONFIG_ARM64
498 	if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) {
499 		start = gd->bd->bi_dram[i - 2].start;
500 		size = gd->bd->bi_dram[i - 2].size;
501 	}
502 
503 	if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M))
504 		size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start;
505 #endif
506 	sprintf(bootm_low, "0x%llx", start);
507 	sprintf(bootm_mapsize, "0x%llx", size);
508 	env_set("bootm_low", bootm_low);
509 	env_set("bootm_mapsize", bootm_mapsize);
510 }
511 #endif
512 
513 #ifdef CONFIG_BIDRAM
514 int board_bidram_reserve(struct bidram *bidram)
515 {
516 	struct memblock mem;
517 	int ret;
518 
519 	/* ATF */
520 	mem = param_parse_atf_mem();
521 	ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size);
522 	if (ret)
523 		return ret;
524 
525 	/* PSTORE/ATAGS/SHM */
526 	mem = param_parse_common_resv_mem();
527 	ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size);
528 	if (ret)
529 		return ret;
530 
531 	/* OP-TEE */
532 	mem = param_parse_optee_mem();
533 	ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size);
534 	if (ret)
535 		return ret;
536 
537 	return 0;
538 }
539 
540 parse_fn_t board_bidram_parse_fn(void)
541 {
542 	return param_parse_ddr_mem;
543 }
544 #endif
545 
546 #ifdef CONFIG_ROCKCHIP_AMP
547 void cpu_secondary_init_r(void)
548 {
549 	amp_cpus_on();
550 }
551 #endif
552 
553 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
554     defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
555 int board_init_f_init_serial(void)
556 {
557 	struct tag *t = atags_get_tag(ATAG_SERIAL);
558 
559 	if (t) {
560 		gd->serial.using_pre_serial = t->u.serial.enable;
561 		gd->serial.addr = t->u.serial.addr;
562 		gd->serial.baudrate = t->u.serial.baudrate;
563 		gd->serial.id = t->u.serial.id;
564 
565 		debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n",
566 		      __func__, gd->serial.using_pre_serial,
567 		      gd->serial.addr, gd->serial.baudrate,
568 		      gd->serial.id);
569 	}
570 
571 	return 0;
572 }
573 #endif
574 
575 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
576 #include <fdt_support.h>
577 #include <usb.h>
578 #include <usb/dwc2_udc.h>
579 
580 static struct dwc2_plat_otg_data otg_data = {
581 	.rx_fifo_sz	= 512,
582 	.np_tx_fifo_sz	= 16,
583 	.tx_fifo_sz	= 128,
584 };
585 
586 int board_usb_init(int index, enum usb_init_type init)
587 {
588 	int node;
589 	fdt_addr_t addr;
590 	const fdt32_t *reg;
591 	const void *blob = gd->fdt_blob;
592 
593 	/* find the usb_otg node */
594 	node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
595 
596 retry:
597 	if (node > 0) {
598 		reg = fdt_getprop(blob, node, "reg", NULL);
599 		if (!reg)
600 			return -EINVAL;
601 
602 		addr = fdt_translate_address(blob, node, reg);
603 		if (addr == OF_BAD_ADDR) {
604 			pr_err("Not found usb_otg address\n");
605 			return -EINVAL;
606 		}
607 
608 #if defined(CONFIG_ROCKCHIP_RK3288)
609 		if (addr != 0xff580000) {
610 			node = fdt_node_offset_by_compatible(blob, node,
611 							     "snps,dwc2");
612 			goto retry;
613 		}
614 #endif
615 	} else {
616 		/*
617 		 * With kernel dtb support, rk3288 dwc2 otg node
618 		 * use the rockchip legacy dwc2 driver "dwc_otg_310"
619 		 * with the compatible "rockchip,rk3288_usb20_otg",
620 		 * and rk3368 also use the "dwc_otg_310" driver with
621 		 * the compatible "rockchip,rk3368-usb".
622 		 */
623 #if defined(CONFIG_ROCKCHIP_RK3288)
624 		node = fdt_node_offset_by_compatible(blob, -1,
625 				"rockchip,rk3288_usb20_otg");
626 #elif defined(CONFIG_ROCKCHIP_RK3368)
627 		node = fdt_node_offset_by_compatible(blob, -1,
628 				"rockchip,rk3368-usb");
629 #endif
630 		if (node > 0) {
631 			goto retry;
632 		} else {
633 			pr_err("Not found usb_otg device\n");
634 			return -ENODEV;
635 		}
636 	}
637 
638 	otg_data.regs_otg = (uintptr_t)addr;
639 
640 	return dwc2_udc_probe(&otg_data);
641 }
642 
643 int board_usb_cleanup(int index, enum usb_init_type init)
644 {
645 	return 0;
646 }
647 #endif
648