1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <amp.h> 9 #include <bidram.h> 10 #include <boot_rkimg.h> 11 #include <cli.h> 12 #include <clk.h> 13 #include <console.h> 14 #include <debug_uart.h> 15 #include <dm.h> 16 #include <dvfs.h> 17 #include <io-domain.h> 18 #include <key.h> 19 #include <memblk.h> 20 #include <misc.h> 21 #include <of_live.h> 22 #include <ram.h> 23 #include <rockchip_debugger.h> 24 #include <syscon.h> 25 #include <sysmem.h> 26 #include <video_rockchip.h> 27 #include <asm/io.h> 28 #include <asm/gpio.h> 29 #include <dm/uclass-internal.h> 30 #include <dm/root.h> 31 #include <power/charge_display.h> 32 #include <power/regulator.h> 33 #include <asm/arch/boot_mode.h> 34 #include <asm/arch/clock.h> 35 #include <asm/arch/cpu.h> 36 #include <asm/arch/hotkey.h> 37 #include <asm/arch/param.h> 38 #include <asm/arch/periph.h> 39 #include <asm/arch/resource_img.h> 40 #include <asm/arch/rk_atags.h> 41 #include <asm/arch/vendor.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 __weak int rk_board_late_init(void) 46 { 47 return 0; 48 } 49 50 __weak int rk_board_fdt_fixup(void *blob) 51 { 52 return 0; 53 } 54 55 __weak int soc_clk_dump(void) 56 { 57 return 0; 58 } 59 60 __weak int set_armclk_rate(void) 61 { 62 return 0; 63 } 64 65 __weak int rk_board_init(void) 66 { 67 return 0; 68 } 69 70 /* 71 * define serialno max length, the max length is 512 Bytes 72 * The remaining bytes are used to ensure that the first 512 bytes 73 * are valid when executing 'env_set("serial#", value)'. 74 */ 75 #define VENDOR_SN_MAX 513 76 #define CPUID_LEN 0x10 77 #define CPUID_OFF 0x07 78 79 static int rockchip_set_ethaddr(void) 80 { 81 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 82 char buf[ARP_HLEN_ASCII + 1]; 83 u8 ethaddr[ARP_HLEN]; 84 int ret; 85 86 ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr)); 87 if (ret > 0 && is_valid_ethaddr(ethaddr)) { 88 sprintf(buf, "%pM", ethaddr); 89 env_set("ethaddr", buf); 90 } 91 #endif 92 return 0; 93 } 94 95 static int rockchip_set_serialno(void) 96 { 97 u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2]; 98 u8 cpuid[CPUID_LEN] = {0}; 99 char serialno_str[VENDOR_SN_MAX]; 100 int ret = 0, i; 101 u64 serialno; 102 103 /* Read serial number from vendor storage part */ 104 memset(serialno_str, 0, VENDOR_SN_MAX); 105 106 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 107 ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1)); 108 if (ret > 0) { 109 env_set("serial#", serialno_str); 110 } else { 111 #endif 112 #ifdef CONFIG_ROCKCHIP_EFUSE 113 struct udevice *dev; 114 115 /* retrieve the device */ 116 ret = uclass_get_device_by_driver(UCLASS_MISC, 117 DM_GET_DRIVER(rockchip_efuse), 118 &dev); 119 if (ret) { 120 printf("%s: could not find efuse device\n", __func__); 121 return ret; 122 } 123 124 /* read the cpu_id range from the efuses */ 125 ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid)); 126 if (ret) { 127 printf("%s: read cpuid from efuses failed, ret=%d\n", 128 __func__, ret); 129 return ret; 130 } 131 #else 132 /* generate random cpuid */ 133 for (i = 0; i < CPUID_LEN; i++) 134 cpuid[i] = (u8)(rand()); 135 #endif 136 /* Generate the serial number based on CPU ID */ 137 for (i = 0; i < 8; i++) { 138 low[i] = cpuid[1 + (i << 1)]; 139 high[i] = cpuid[i << 1]; 140 } 141 142 serialno = crc32_no_comp(0, low, 8); 143 serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; 144 snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); 145 146 env_set("serial#", serialno_str); 147 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 148 } 149 #endif 150 151 return ret; 152 } 153 154 #if defined(CONFIG_USB_FUNCTION_FASTBOOT) 155 int fb_set_reboot_flag(void) 156 { 157 printf("Setting reboot to fastboot flag ...\n"); 158 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); 159 160 return 0; 161 } 162 #endif 163 164 #ifdef CONFIG_ROCKCHIP_USB_BOOT 165 static int boot_from_udisk(void) 166 { 167 struct blk_desc *desc; 168 char *devtype; 169 char *devnum; 170 171 devtype = env_get("devtype"); 172 devnum = env_get("devnum"); 173 174 /* Booting priority: mmc1 > udisk */ 175 if (!strcmp(devtype, "mmc") && !strcmp(devnum, "1")) 176 return 0; 177 178 if (!run_command("usb start", -1)) { 179 desc = blk_get_devnum_by_type(IF_TYPE_USB, 0); 180 if (!desc) { 181 printf("No usb device found\n"); 182 return -ENODEV; 183 } 184 185 if (!run_command("rkimgtest usb 0", -1)) { 186 rockchip_set_bootdev(desc); 187 env_set("devtype", "usb"); 188 env_set("devnum", "0"); 189 env_set("reboot_mode", "recovery-usb"); 190 printf("Boot from usb 0\n"); 191 } else { 192 printf("No usb dev 0 found\n"); 193 return -ENODEV; 194 } 195 } 196 197 return 0; 198 } 199 #endif 200 201 int board_late_init(void) 202 { 203 rockchip_set_ethaddr(); 204 rockchip_set_serialno(); 205 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 206 setup_boot_mode(); 207 #endif 208 #ifdef CONFIG_ROCKCHIP_USB_BOOT 209 boot_from_udisk(); 210 #endif 211 #ifdef CONFIG_DM_CHARGE_DISPLAY 212 charge_display(); 213 #endif 214 #ifdef CONFIG_DRM_ROCKCHIP 215 rockchip_show_logo(); 216 #endif 217 soc_clk_dump(); 218 219 return rk_board_late_init(); 220 } 221 222 #ifdef CONFIG_USING_KERNEL_DTB 223 /* Here, only fixup cru phandle, pmucru is not included */ 224 static int phandles_fixup(void *fdt) 225 { 226 const char *props[] = { "clocks", "assigned-clocks" }; 227 struct udevice *dev; 228 struct uclass *uc; 229 const char *comp; 230 u32 id, nclocks; 231 u32 *clocks; 232 int phandle, ncells; 233 int off, offset; 234 int ret, length; 235 int i, j; 236 int first_phandle = -1; 237 238 phandle = -ENODATA; 239 ncells = -ENODATA; 240 241 /* fdt points to kernel dtb, getting cru phandle and "#clock-cells" */ 242 for (offset = fdt_next_node(fdt, 0, NULL); 243 offset >= 0; 244 offset = fdt_next_node(fdt, offset, NULL)) { 245 comp = fdt_getprop(fdt, offset, "compatible", NULL); 246 if (!comp) 247 continue; 248 249 /* Actually, this is not a good method to get cru node */ 250 off = strlen(comp) - strlen("-cru"); 251 if (off > 0 && !strncmp(comp + off, "-cru", 4)) { 252 phandle = fdt_get_phandle(fdt, offset); 253 ncells = fdtdec_get_int(fdt, offset, 254 "#clock-cells", -ENODATA); 255 break; 256 } 257 } 258 259 if (phandle == -ENODATA || ncells == -ENODATA) 260 return 0; 261 262 debug("%s: target cru: clock-cells:%d, phandle:0x%x\n", 263 __func__, ncells, fdt32_to_cpu(phandle)); 264 265 /* Try to fixup all cru phandle from U-Boot dtb nodes */ 266 for (id = 0; id < UCLASS_COUNT; id++) { 267 ret = uclass_get(id, &uc); 268 if (ret) 269 continue; 270 271 if (list_empty(&uc->dev_head)) 272 continue; 273 274 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 275 /* Only U-Boot node go further */ 276 if (!dev_read_bool(dev, "u-boot,dm-pre-reloc") || 277 !dev_read_bool(dev, "u-boot,dm-spl")) 278 continue; 279 280 for (i = 0; i < ARRAY_SIZE(props); i++) { 281 if (!dev_read_prop(dev, props[i], &length)) 282 continue; 283 284 clocks = malloc(length); 285 if (!clocks) 286 return -ENOMEM; 287 288 /* Read "props[]" which contains cru phandle */ 289 nclocks = length / sizeof(u32); 290 if (dev_read_u32_array(dev, props[i], 291 clocks, nclocks)) { 292 free(clocks); 293 continue; 294 } 295 296 /* Fixup with kernel cru phandle */ 297 for (j = 0; j < nclocks; j += (ncells + 1)) { 298 /* 299 * Check: update pmucru phandle with cru 300 * phandle by mistake. 301 */ 302 if (first_phandle == -1) 303 first_phandle = clocks[j]; 304 305 if (clocks[j] != first_phandle) { 306 debug("WARN: %s: first cru phandle=%d, this=%d\n", 307 dev_read_name(dev), 308 first_phandle, clocks[j]); 309 continue; 310 } 311 312 clocks[j] = phandle; 313 } 314 315 /* 316 * Override live dt nodes but not fdt nodes, 317 * because all U-Boot nodes has been imported 318 * to live dt nodes, should use "dev_xxx()". 319 */ 320 dev_write_u32_array(dev, props[i], 321 clocks, nclocks); 322 free(clocks); 323 } 324 } 325 } 326 327 return 0; 328 } 329 330 int init_kernel_dtb(void) 331 { 332 ulong fdt_addr; 333 int ret; 334 335 fdt_addr = env_get_ulong("fdt_addr_r", 16, 0); 336 if (!fdt_addr) { 337 printf("No Found FDT Load Address.\n"); 338 return -1; 339 } 340 341 ret = rockchip_read_dtb_file((void *)fdt_addr); 342 if (ret < 0) { 343 if (!fdt_check_header(gd->fdt_blob_kern)) { 344 fdt_addr = (ulong)memalign(ARCH_DMA_MINALIGN, 345 fdt_totalsize(gd->fdt_blob_kern)); 346 if (!fdt_addr) 347 return -ENOMEM; 348 349 memcpy((void *)fdt_addr, gd->fdt_blob_kern, 350 fdt_totalsize(gd->fdt_blob_kern)); 351 printf("DTB: embedded kern.dtb\n"); 352 } else { 353 printf("Failed to get kernel dtb, ret=%d\n", ret); 354 return ret; 355 } 356 } 357 358 gd->fdt_blob = (void *)fdt_addr; 359 360 /* 361 * There is a phandle miss match between U-Boot and kernel dtb node, 362 * the typical is cru phandle, we fixup it in U-Boot live dt nodes. 363 */ 364 phandles_fixup((void *)gd->fdt_blob); 365 366 of_live_build((void *)gd->fdt_blob, (struct device_node **)&gd->of_root); 367 dm_scan_fdt((void *)gd->fdt_blob, false); 368 369 /* Reserve 'reserved-memory' */ 370 ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob); 371 if (ret) 372 return ret; 373 374 return 0; 375 } 376 #endif 377 378 void board_env_fixup(void) 379 { 380 struct memblock mem; 381 ulong u_addr_r; 382 phys_size_t end; 383 char *addr_r; 384 385 #ifdef ENV_MEM_LAYOUT_SETTINGS1 386 const char *env_addr0[] = { 387 "scriptaddr", "pxefile_addr_r", 388 "fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r", 389 }; 390 const char *env_addr1[] = { 391 "scriptaddr1", "pxefile_addr1_r", 392 "fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r", 393 }; 394 int i; 395 396 /* 128M is a typical ram size for most platform, so as default here */ 397 if (gd->ram_size <= SZ_128M) { 398 /* Replace orignal xxx_addr_r */ 399 for (i = 0; i < ARRAY_SIZE(env_addr1); i++) { 400 addr_r = env_get(env_addr1[i]); 401 if (addr_r) 402 env_set(env_addr0[i], addr_r); 403 } 404 } 405 #endif 406 /* If bl32 is disabled, maybe kernel can be load to lower address. */ 407 if (!(gd->flags & GD_FLG_BL32_ENABLED)) { 408 addr_r = env_get("kernel_addr_no_bl32_r"); 409 if (addr_r) 410 env_set("kernel_addr_r", addr_r); 411 /* If bl32 is enlarged, we move ramdisk addr right behind it */ 412 } else { 413 mem = param_parse_optee_mem(); 414 end = mem.base + mem.size; 415 u_addr_r = env_get_ulong("ramdisk_addr_r", 16, 0); 416 if (u_addr_r >= mem.base && u_addr_r < end) 417 env_set_hex("ramdisk_addr_r", end); 418 } 419 } 420 421 static void early_download_init(void) 422 { 423 #if defined(CONFIG_PWRKEY_DNL_TRIGGER_NUM) && \ 424 (CONFIG_PWRKEY_DNL_TRIGGER_NUM > 0) 425 if (pwrkey_download_init()) 426 printf("Pwrkey download init failed\n"); 427 #endif 428 429 if (!tstc()) 430 return; 431 432 gd->console_evt = getc(); 433 if (gd->console_evt <= 0x1a) /* 'z' */ 434 printf("Hotkey: ctrl+%c\n", (gd->console_evt + 'a' - 1)); 435 436 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 437 if (is_hotkey(HK_BROM_DNL)) { 438 printf("Enter bootrom download..."); 439 flushc(); 440 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 441 do_reset(NULL, 0, 0, NULL); 442 printf("failed!\n"); 443 } 444 #endif 445 } 446 447 int board_init(void) 448 { 449 board_debug_uart_init(); 450 451 #ifdef CONFIG_USING_KERNEL_DTB 452 init_kernel_dtb(); 453 #endif 454 early_download_init(); 455 456 /* 457 * pmucru isn't referenced on some platforms, so pmucru driver can't 458 * probe that the "assigned-clocks" is unused. 459 */ 460 clks_probe(); 461 #ifdef CONFIG_DM_REGULATOR 462 if (regulators_enable_boot_on(is_hotkey(HK_REGULATOR))) 463 debug("%s: Can't enable boot on regulator\n", __func__); 464 #endif 465 466 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 467 io_domain_init(); 468 #endif 469 470 set_armclk_rate(); 471 472 #ifdef CONFIG_DM_DVFS 473 dvfs_init(true); 474 #endif 475 476 return rk_board_init(); 477 } 478 479 int interrupt_debugger_init(void) 480 { 481 #ifdef CONFIG_ROCKCHIP_DEBUGGER 482 return rockchip_debugger_init(); 483 #else 484 return 0; 485 #endif 486 } 487 488 int board_fdt_fixup(void *blob) 489 { 490 /* Common fixup for DRM */ 491 #ifdef CONFIG_DRM_ROCKCHIP 492 rockchip_display_fixup(blob); 493 #endif 494 495 return rk_board_fdt_fixup(blob); 496 } 497 498 #ifdef CONFIG_ARM64_BOOT_AARCH32 499 /* 500 * Fixup MMU region attr for OP-TEE on ARMv8 CPU: 501 * 502 * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode. 503 * 504 * Command for OP-TEE: 505 * 64-bit mode: dcache is always enabled; 506 * 32-bit mode: dcache is always disabled(Due to some unknown issue); 507 * 508 * Command for U-Boot: 509 * 64-bit mode: MMU table is static defined in rkxxx.c file, all memory 510 * regions are mapped. That's good to match OP-TEE MMU policy. 511 * 512 * 32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where 513 * the OP-TEE region has been reserved, so it can not be 514 * mapped(i.e. dcache is disabled). That's also good to match 515 * OP-TEE MMU policy. 516 * 517 * For the data coherence when communication between U-Boot and OP-TEE, U-Boot 518 * should follow OP-TEE MMU policy. 519 * 520 * Here is the special: 521 * When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while 522 * OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE 523 * region(but OP-TEE requires it cacheable) so we fixup here. 524 */ 525 int board_initr_caches_fixup(void) 526 { 527 struct memblock mem; 528 529 mem = param_parse_optee_mem(); 530 if (mem.size) 531 mmu_set_region_dcache_behaviour(mem.base, mem.size, 532 DCACHE_WRITEBACK); 533 return 0; 534 } 535 #endif 536 537 void arch_preboot_os(uint32_t bootm_state) 538 { 539 if (bootm_state & BOOTM_STATE_OS_PREP) 540 hotkey_run(HK_CLI_OS_PRE); 541 } 542 543 void board_quiesce_devices(void) 544 { 545 hotkey_run(HK_CMDLINE); 546 hotkey_run(HK_CLI_OS_GO); 547 548 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 549 /* Destroy atags makes next warm boot safer */ 550 atags_destroy(); 551 #endif 552 553 #if defined(CONFIG_CONSOLE_RECORD) 554 /* Print record console data */ 555 console_record_print_purge(); 556 #endif 557 } 558 559 void enable_caches(void) 560 { 561 icache_enable(); 562 dcache_enable(); 563 } 564 565 #ifdef CONFIG_LMB 566 /* 567 * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". 568 * This makes lmb_alloc_base() always alloc from tail of sdram. 569 * If we don't assign it, bi_dram[0] is used by default and it may cause 570 * lmb_alloc_base() fail when bi_dram[0] range is small. 571 */ 572 void board_lmb_reserve(struct lmb *lmb) 573 { 574 char bootm_mapsize[32]; 575 char bootm_low[32]; 576 u64 start, size; 577 int i; 578 579 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 580 if (!gd->bd->bi_dram[i].size) 581 break; 582 } 583 584 start = gd->bd->bi_dram[i - 1].start; 585 size = gd->bd->bi_dram[i - 1].size; 586 587 /* 588 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+), 589 * otherwise "Unable to handle kernel paging request at virtual address ...". 590 * 591 * So that we hope limit highest address at 768M, but there comes the the 592 * problem: ramdisk is a compressed image and it expands after descompress, 593 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...". 594 * 595 * We make a appointment that the highest memory address is 512MB, it 596 * makes lmb alloc safer. 597 */ 598 #ifndef CONFIG_ARM64 599 if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) { 600 start = gd->bd->bi_dram[i - 2].start; 601 size = gd->bd->bi_dram[i - 2].size; 602 } 603 604 if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) 605 size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start; 606 #endif 607 sprintf(bootm_low, "0x%llx", start); 608 sprintf(bootm_mapsize, "0x%llx", size); 609 env_set("bootm_low", bootm_low); 610 env_set("bootm_mapsize", bootm_mapsize); 611 } 612 #endif 613 614 #ifdef CONFIG_BIDRAM 615 int board_bidram_reserve(struct bidram *bidram) 616 { 617 struct memblock mem; 618 int ret; 619 620 /* ATF */ 621 mem = param_parse_atf_mem(); 622 ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size); 623 if (ret) 624 return ret; 625 626 /* PSTORE/ATAGS/SHM */ 627 mem = param_parse_common_resv_mem(); 628 ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size); 629 if (ret) 630 return ret; 631 632 /* OP-TEE */ 633 mem = param_parse_optee_mem(); 634 ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size); 635 if (ret) 636 return ret; 637 638 return 0; 639 } 640 641 parse_fn_t board_bidram_parse_fn(void) 642 { 643 return param_parse_ddr_mem; 644 } 645 #endif 646 647 #ifdef CONFIG_ROCKCHIP_AMP 648 void cpu_secondary_init_r(void) 649 { 650 amp_cpus_on(); 651 } 652 #endif 653 654 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 655 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 656 int board_init_f_init_serial(void) 657 { 658 struct tag *t = atags_get_tag(ATAG_SERIAL); 659 660 if (t) { 661 gd->serial.using_pre_serial = t->u.serial.enable; 662 gd->serial.addr = t->u.serial.addr; 663 gd->serial.baudrate = t->u.serial.baudrate; 664 gd->serial.id = t->u.serial.id; 665 666 debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 667 __func__, gd->serial.using_pre_serial, 668 gd->serial.addr, gd->serial.baudrate, 669 gd->serial.id); 670 } 671 672 return 0; 673 } 674 #endif 675 676 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 677 #include <fdt_support.h> 678 #include <usb.h> 679 #include <usb/dwc2_udc.h> 680 681 static struct dwc2_plat_otg_data otg_data = { 682 .rx_fifo_sz = 512, 683 .np_tx_fifo_sz = 16, 684 .tx_fifo_sz = 128, 685 }; 686 687 int board_usb_init(int index, enum usb_init_type init) 688 { 689 const void *blob = gd->fdt_blob; 690 const fdt32_t *reg; 691 fdt_addr_t addr; 692 int node; 693 694 /* find the usb_otg node */ 695 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 696 697 retry: 698 if (node > 0) { 699 reg = fdt_getprop(blob, node, "reg", NULL); 700 if (!reg) 701 return -EINVAL; 702 703 addr = fdt_translate_address(blob, node, reg); 704 if (addr == OF_BAD_ADDR) { 705 pr_err("Not found usb_otg address\n"); 706 return -EINVAL; 707 } 708 709 #if defined(CONFIG_ROCKCHIP_RK3288) 710 if (addr != 0xff580000) { 711 node = fdt_node_offset_by_compatible(blob, node, 712 "snps,dwc2"); 713 goto retry; 714 } 715 #endif 716 } else { 717 /* 718 * With kernel dtb support, rk3288 dwc2 otg node 719 * use the rockchip legacy dwc2 driver "dwc_otg_310" 720 * with the compatible "rockchip,rk3288_usb20_otg", 721 * and rk3368 also use the "dwc_otg_310" driver with 722 * the compatible "rockchip,rk3368-usb". 723 */ 724 #if defined(CONFIG_ROCKCHIP_RK3288) 725 node = fdt_node_offset_by_compatible(blob, -1, 726 "rockchip,rk3288_usb20_otg"); 727 #elif defined(CONFIG_ROCKCHIP_RK3368) 728 node = fdt_node_offset_by_compatible(blob, -1, 729 "rockchip,rk3368-usb"); 730 #endif 731 if (node > 0) { 732 goto retry; 733 } else { 734 pr_err("Not found usb_otg device\n"); 735 return -ENODEV; 736 } 737 } 738 739 otg_data.regs_otg = (uintptr_t)addr; 740 741 return dwc2_udc_probe(&otg_data); 742 } 743 744 int board_usb_cleanup(int index, enum usb_init_type init) 745 { 746 return 0; 747 } 748 #endif 749